Hybrid Packaged Lead Frame Based Multi-Chip Semiconductor Device with Multiple Interconnecting Structures
Granted: October 27, 2016
Application Number:
20160315039
A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first…
COMBINED PACKAGED POWER SEMICONDUCTOR DEVICE
Granted: October 20, 2016
Application Number:
20160307830
A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally…
POWER DEVICE WITH HIGH ASPECT RATIO TRENCH CONTACTS AND SUBMICRON PITCHES BETWEEN TRENCHES
Granted: July 28, 2016
Application Number:
20160218008
This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The…
SEMICONDUCTOR DEVICE INTEGRATING HIGH AND LOW VOLTAGE DEVICES
Granted: April 7, 2016
Application Number:
20160099310
The present invention is directed to a method for forming multiple active components, such as bipolar transistors. MOSFETs, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components. The present invention is further directed to a method for forming a device of…
EMBEDDED PACKAGE AND METHOD THEREOF
Granted: April 7, 2016
Application Number:
20160099238
The present invention discloses anew embedded package comprising: a pre-mold lead frame with a plurality of chips attached thereon, where the molding material fills the voids of the lead frame, no that the lead frame is entirely solid; a plurality of pins arranged around the lead frame; a metal clip attached on and electrically connecting the chips together; first laminate layer which covers the chips, the lead frame, a metal clip and pins; conductive plug and extension formed to connect…
SEMICONDUCTOR PACKAGE WITH SMALL GATE CLIP AND ASSEMBLY METHOD
Granted: March 31, 2016
Application Number:
20160093559
A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted…
WAFER PROCESS FOR MOLDED CHIP SCALE PACKAGE (MCSP) WITH THICK BACKSIDE METALLIZATION
Granted: March 17, 2016
Application Number:
20160079203
A wafer process for molded chip scale package (MCSP) comprises: depositing metal bumps on bonding pads of chips on a wafer; forming a first packaging layer at a front surface of the wafer to cover the metal bumps; forming an un-covered ring at an edge of the wafer to expose two ends of each scribe line of a plurality of scribe lines; thinning the first packaging layer to expose metal bumps; forming cutting grooves; grinding a back surface of the wafer to form a recessed space and a…
METHOD AND STRUCTURE FOR WAFER LEVEL PACKAGING WITH LARGE CONTACT AREA
Granted: March 3, 2016
Application Number:
20160064251
A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the…
POWER SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF
Granted: February 25, 2016
Application Number:
20160056096
A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with…
INTEGRATING SCHOTTKY DIODE INTO POWER MOSFET
Granted: January 7, 2016
Application Number:
20160005853
A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in…
ALTERNATING CURRENT INJECTION FOR CONSTANT-ON TIME BUCK CONVERTER - A REGULATOR CONTROL METHOD
Granted: December 24, 2015
Application Number:
20150372595
The present invention discloses a voltage control method. At first, the load voltage of the load is divided to generate a feedback voltage. The feedback voltage and a triangular wave of a triangular wave periodic signal, including the positive voltage and negative voltage, are combined to generate a sum signal. The sum signal is compared with a target voltage, and when the sum signal is less than the target voltage signal, a control signal is generated to control the switches to turn on…
POWER SEMICONDUCTOR DEVICE WITH SMALL CONTACT FOOTPRINT AND THE PREPARATION METHOD
Granted: December 10, 2015
Application Number:
20150357268
A power semiconductor package with a small footprint and a preparation method thereof are disclosed. The first semiconductor chip and second semiconductor chip are attached on the front and back sides of a die paddle. Conductive pads are then attached on the electrodes at the top surfaces of the first and second semiconductor chips flowed by the formation of a plastic package body covering the die paddle, first and second semiconductor chips, the conductive pads, where a side surface of…
COMBINED PACKAGED POWER SEMICONDUCTOR DEVICE
Granted: December 10, 2015
Application Number:
20150357267
A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally…
INJECTION CONTROL IN SEMICONDUCTOR POWER DEVICES
Granted: December 3, 2015
Application Number:
20150349101
Semiconductor power devices can be formed on substrate structure having a lightly doped semiconductor substrate of a first conductivity type or a second conductivity type opposite to the first conductivity type. A semiconductive first buffer layer of the first conductivity type formed above the substrate. A doping concentration of the first buffer layer is greater than a doping concentration of the substrate. A second buffer layer of the second conductivity type formed above the first…
HIGH DENSITY MOSFET ARRAY WITH SELF-ALIGNED CONTACTS DELIMITED BY NITRIDE-CAPPED TRENCH GATE STACKS AND METHOD
Granted: November 26, 2015
Application Number:
20150340363
A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to…
EMBEDDED PACKAGE AND METHOD THEREOF
Granted: November 12, 2015
Application Number:
20150325559
The present invention discloses a new embedded package comprising: a pre-mold lead frame with a plurality of chips attached thereon, where the molding material fills the voids of the lead frame, so that the lead frame is entirely solid; a plurality of pins arranged around the lead frame; a metal clip attached on and electrically connecting the chips together; first laminate layer which covers the chips, the lead frame, a metal clip and pins; conductive plug and extension formed to…
ULTRA-THIN SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF
Granted: November 12, 2015
Application Number:
20150325500
A small and ultra-thin power semiconductor device and a preparation method are disclosed. The device includes a chip mounting unit with a plurality of pads with a plate arranged on top surface of each pad; a semiconductor chip flipped and attached on the chip mounting unit, where the electrodes at the front of the chip are electrically connected to the pads; a plastic packaging body covering the chip mounting units and the chip, where the top surface of the plate and the back surface of…
SPLIT POLY CONNECTION VIA THROUGH-POLY-CONTACT (TPC) IN SPLIT-GATE BASED POWER MOSFETS
Granted: October 29, 2015
Application Number:
20150311295
Embodiments of the present disclosure provide a contact structure in a split-gate trench transistor device for electrically connecting the top electrode to the bottom electrode inside the trench. The transistor device comprises a semiconductor substrate and one or more trenches formed in the semiconductor substrate. The trenches are lined with insulating materials along the sidewalls inside the trenches. Each trench has a bottom electrode in lower portions of the trench and a top…
MOSFET SWITCH CIRCUIT FOR SLOW SWITCHING APPLICATION
Granted: October 15, 2015
Application Number:
20150295495
A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal. The first and second MOS transistors have respective gate terminals coupled to the control terminal to receive a control signal to turn the switch circuit on or off where the control signal transitions from a first voltage level to a second voltage level at a slow rate of change. The first MOS transistor has a first…
CLOSED CELL LATERAL MOSFET USING SILICIDE SOURCE AND BODY REGIONS
Granted: October 8, 2015
Application Number:
20150287820
A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in one or more source cells with silicided source and body diffusion regions formed therein. In this manner, the cell pitch of the cellular transistor array is kept small while the ruggedness of the transistor is ensured. In other embodiments, a closed cell lateral MOSFET device is formed using silicided source and body diffusion regions and self-aligned contacts or borderless contacts as the…
