BATTERY PROTECTION PACKAGE AND PROCESS OF MAKING THE SAME
Granted: February 2, 2017
Application Number:
20170033060
The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and…
METHOD AND STRUCTURE FOR WAFER LEVEL PACKAGING WITH LARGE CONTACT AREA
Granted: January 26, 2017
Application Number:
20170025356
A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the…
SEMICONDUCTOR PACKAGE WITH SMALL GATE CLIP AND ASSEMBLY METHOD
Granted: December 29, 2016
Application Number:
20160379918
A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted…
POWER SEMICONDUCTOR PACKAGE DEVICE HAVING LOCKING MECHANISM, AND PREPARATION METHOD THEREOF
Granted: December 29, 2016
Application Number:
20160379917
A power semiconductor package device and a method of preparation the device are disclosed. The package device includes a die paddle, a first pin, a second pin, and a semiconductor chip attached to the die paddle. A first electrode, a second electrode and a third electrode of the semiconductor chip are connected to the first pin, the second pin and the die paddle respectively. A plastic package body covers the semiconductor chip, the die paddle, the first pin and the second pin. The first…
POWER SUPPLY DEVICE
Granted: December 8, 2016
Application Number:
20160359421
The present invention relates to a power supply device for voltage converter, which includes a master switch, a first controller for generating a first pulse signal to drive the master switch to be turned on and turned off, a second controller for comparing a detection voltage representing an output voltage and/or load current with a first reference voltage to determine the logic state of a control signal generated by the second controller, and a coupling element connected between the…
VOLTAGE CONVERTER
Granted: December 8, 2016
Application Number:
20160359419
A voltage converter comprises a second controller as a power switch of the secondary side of the transformer for comparing a detection voltage representing an output voltage and/or load current with a first reference voltage and generating a control signal, and a coupling element for transmitting the control signal generated by the second controller to the first controller on the primary side of the transformer enabling the first controller to generate a first pulse signal driving the…
NOVEL PULSE TRANSFORMER
Granted: December 8, 2016
Application Number:
20160358705
A voltage converter comprises a second controller as a power switch of the secondary side of the transformer for comparing a detection voltage representing an output voltage and/or load current with a first reference voltage and generating a control signal, and a coupling element for transmitting the control signal generated by the second controller to the first controller on the primary side of the transformer enabling the first controller to generate a first pulse signal driving the…
Hybrid Packaged Lead Frame Based Multi-Chip Semiconductor Device with Multiple Interconnecting Structures
Granted: October 27, 2016
Application Number:
20160315039
A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first…
COMBINED PACKAGED POWER SEMICONDUCTOR DEVICE
Granted: October 20, 2016
Application Number:
20160307830
A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally…
POWER DEVICE WITH HIGH ASPECT RATIO TRENCH CONTACTS AND SUBMICRON PITCHES BETWEEN TRENCHES
Granted: July 28, 2016
Application Number:
20160218008
This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The…
SEMICONDUCTOR DEVICE INTEGRATING HIGH AND LOW VOLTAGE DEVICES
Granted: April 7, 2016
Application Number:
20160099310
The present invention is directed to a method for forming multiple active components, such as bipolar transistors. MOSFETs, diodes, etc., on a semiconductor substrate so that active components with higher operation voltage may be formed on a common substrate with a lower operation voltage device and incorporating the existing proven process flow of making the lower operation voltage active components. The present invention is further directed to a method for forming a device of…
EMBEDDED PACKAGE AND METHOD THEREOF
Granted: April 7, 2016
Application Number:
20160099238
The present invention discloses anew embedded package comprising: a pre-mold lead frame with a plurality of chips attached thereon, where the molding material fills the voids of the lead frame, no that the lead frame is entirely solid; a plurality of pins arranged around the lead frame; a metal clip attached on and electrically connecting the chips together; first laminate layer which covers the chips, the lead frame, a metal clip and pins; conductive plug and extension formed to connect…
SEMICONDUCTOR PACKAGE WITH SMALL GATE CLIP AND ASSEMBLY METHOD
Granted: March 31, 2016
Application Number:
20160093559
A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted…
WAFER PROCESS FOR MOLDED CHIP SCALE PACKAGE (MCSP) WITH THICK BACKSIDE METALLIZATION
Granted: March 17, 2016
Application Number:
20160079203
A wafer process for molded chip scale package (MCSP) comprises: depositing metal bumps on bonding pads of chips on a wafer; forming a first packaging layer at a front surface of the wafer to cover the metal bumps; forming an un-covered ring at an edge of the wafer to expose two ends of each scribe line of a plurality of scribe lines; thinning the first packaging layer to expose metal bumps; forming cutting grooves; grinding a back surface of the wafer to form a recessed space and a…
METHOD AND STRUCTURE FOR WAFER LEVEL PACKAGING WITH LARGE CONTACT AREA
Granted: March 3, 2016
Application Number:
20160064251
A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the…
POWER SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF
Granted: February 25, 2016
Application Number:
20160056096
A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with…
INTEGRATING SCHOTTKY DIODE INTO POWER MOSFET
Granted: January 7, 2016
Application Number:
20160005853
A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in…
ALTERNATING CURRENT INJECTION FOR CONSTANT-ON TIME BUCK CONVERTER - A REGULATOR CONTROL METHOD
Granted: December 24, 2015
Application Number:
20150372595
The present invention discloses a voltage control method. At first, the load voltage of the load is divided to generate a feedback voltage. The feedback voltage and a triangular wave of a triangular wave periodic signal, including the positive voltage and negative voltage, are combined to generate a sum signal. The sum signal is compared with a target voltage, and when the sum signal is less than the target voltage signal, a control signal is generated to control the switches to turn on…
COMBINED PACKAGED POWER SEMICONDUCTOR DEVICE
Granted: December 10, 2015
Application Number:
20150357267
A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally…
POWER SEMICONDUCTOR DEVICE WITH SMALL CONTACT FOOTPRINT AND THE PREPARATION METHOD
Granted: December 10, 2015
Application Number:
20150357268
A power semiconductor package with a small footprint and a preparation method thereof are disclosed. The first semiconductor chip and second semiconductor chip are attached on the front and back sides of a die paddle. Conductive pads are then attached on the electrodes at the top surfaces of the first and second semiconductor chips flowed by the formation of a plastic package body covering the die paddle, first and second semiconductor chips, the conductive pads, where a side surface of…
