Uni-directional transient voltage suppressor (TVS)
Granted: May 22, 2018
Patent Number:
9978740
A unidirectional transient voltage suppressor (TVS) device is formed with first and second NPN transistors that are connected in parallel to each other. Each NPN transistor includes a collector region, an emitter. The first and second NPN structures are formed on a common substrate. The first NPN transistor has a floating base and the second NPN transistor has a base shorted to an emitter.
Semiconductor power device having single in-line lead module and method of making the same
Granted: May 8, 2018
Patent Number:
9966328
A semiconductor power device is disclosed. The semiconductor power device comprises a lead frame unit, two or more pluralities of single in-line leads, two or more semiconductor chip stacks, and a molding encapsulation. Each semiconductor chip stack includes a high-side semiconductor chip, a low-side semiconductor chip and a clip connecting a top surface of the high-side semiconductor chip to a bottom surface of the low-side semiconductor chip. This invention further discloses a method…
Voltage converter
Granted: May 1, 2018
Patent Number:
9960664
A voltage converter comprises a second controller as a power switch of the secondary side of the transformer for comparing a detection voltage representing an output voltage and/or load current with a first reference voltage and generating a control signal, and a coupling element for transmitting the control signal generated by the second controller to the first controller on the primary side of the transformer enabling the first controller to generate a first pulse signal driving the…
Termination structure with multiple embedded potential spreading capacitive structures for trench MOSFET
Granted: May 1, 2018
Patent Number:
9960237
A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT…
Method and structure for wafer level packaging with large contact area
Granted: May 1, 2018
Patent Number:
9960119
A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the…
Constant on time COT control in isolated converter
Granted: April 24, 2018
Patent Number:
9954455
The present invention discloses a constant on-time isolated converter comprising a transformer with a primary side and a secondary side. The primary side is connected to an electronic switch and secondary-side is connected to a load and a processor. The processor is connected to a driver on primary side through at least one coupling element and to the electronic switch. The processor receives an output voltage or an output current across the load generating a control signal accordingly.…
Flyback converter output current evaluation circuit and evaluation method
Granted: April 24, 2018
Patent Number:
9954449
An output current calculating circuit for a flyback converter operating under CCM and DCM is disclosed. The off current value IOFF and the blanking current value ILEB flowing through a sensing resistor are calculated using a detection module and are summed together using a current summing unit. A voltage converted from the sum value of the off current value IOFF and the blanking current value ILEB is transmitted through an output stage in a predetermined time ratio of a cycle with the…
Semiconductor package of a flipped MOSFET chip and a multi-based die paddle with top surface groove-divided multiple connecting areas for connection to the flipped MOSFET electrodes
Granted: March 27, 2018
Patent Number:
9929076
The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple…
Transient voltage suppressor (TVS) with reduced breakdown voltage
Granted: March 6, 2018
Patent Number:
9911728
A low capacitance transient voltage suppressor with snapback control and a reduced voltage punch-through breakdown mode includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A set of source regions is formed within a top…
Self aligned trench MOSFET with integrated diode
Granted: March 6, 2018
Patent Number:
9911840
A transistor device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator portions are formed over the gate electrodes on a top surface of the substrate…
Zero voltage switching flyback converter for primary switch turn-off transitions
Granted: February 20, 2018
Patent Number:
9899931
A flyback converter implements a Forced Zero Voltage Switching (ZVS) timing control by detecting a positive current excursion of the secondary winding current as the synchronous rectifier turn off trigger. The synchronous rectifier switch is turned on near the end of the switching cycle or the on duration is extended to develop a current ripple on the secondary winding current. The control circuit of the flyback converter detects a positive current excursion on the secondary winding…
Nanotube semiconductor devices
Granted: February 20, 2018
Patent Number:
9899474
Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer formed thereon and of the opposite conductivity type, and a first epitaxial layer formed on mesas of the second semiconductor layer. An electric field along a length of the first epitaxial layer is uniformly distributed.
Compact CMOS device isolation
Granted: February 20, 2018
Patent Number:
9899471
An integrated circuit uses a compact CMOS device isolation scheme which forms a ring of N-well housing PMOS devices to encircle the P-well housing NMOS devices in a circuit block. An N-type buried layer is formed under the P-well and extends partially under the surrounding N-well. The compact CMOS device isolation scheme eliminates the use of a deep N-well ring around the circuit block. Therefore, the circuit blocks of the integrated circuit can be formed with reduced silicon area and…
Cascoded high voltage junction field effect transistor
Granted: February 13, 2018
Patent Number:
9893209
A cascoded junction field transistor (JFET) device comprises a first stage high voltage JFET cascoded to a second stage low voltage JFET wherein one of the first and second stages JFET is connected to a drain electrode of another JFET stage.
Process method and structure for high voltage MOSFETs
Granted: February 6, 2018
Patent Number:
9887283
This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant…
Power supply device
Granted: January 30, 2018
Patent Number:
9882500
The present invention relates to a power supply device for voltage converter, which includes a master switch, a first controller for generating a first pulse signal to drive the master switch to be turned on and turned off, a second controller for comparing a detection voltage representing an output voltage and/or load current with a first reference voltage to determine the logic state of a control signal generated by the second controller, and a coupling element connected between the…
Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method
Granted: January 30, 2018
Patent Number:
9882049
This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation…
Molded intelligent power module
Granted: January 30, 2018
Patent Number:
9881856
An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth transistors, a tie bar, a low voltage IC, a high voltage IC, a first, second and third boost diodes, a plurality of leads and a molding encapsulation. The first transistor is attached to the first die paddle. The second transistor is attached to the second die paddle. The third transistor is attached to the third die paddle. The fourth, fifth and sixth…
Configurations and methods for manufacturing charged balanced devices
Granted: January 23, 2018
Patent Number:
9876072
This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of…
Integrated Schottky diode in high voltage semiconductor device
Granted: January 23, 2018
Patent Number:
9876073
This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide…
