Wafer process for molded chip scale package (MCSP) with thick backside metallization
Granted: December 13, 2016
Patent Number:
9520380
A wafer process for molded chip scale package (MCSP) comprises: depositing metal bumps on bonding pads of chips on a wafer; forming a first packaging layer at a front surface of the wafer to cover the metal bumps; forming an un-covered ring at an edge of the wafer to expose two ends of each scribe line of a plurality of scribe lines; thinning the first packaging layer to expose metal bumps; forming cutting grooves; grinding a back surface of the wafer to form a recessed space and a…
Voltage detection circuit and a method of detecting voltage changes
Granted: December 6, 2016
Patent Number:
9515570
A power conversion system and a method for voltage change detection, specifically, relates to a detection circuit implemented in the AC-DC power converter, detect the voltage change. The AC input voltage is rectified to convert into a DC input voltage transmitted to a detection unit generating a detection voltage signal at different logical states corresponding to the input voltage changes. A charge current source unit is used for charging the capacitor when the detection voltage signal…
Termination design for nanotube MOSFET
Granted: November 29, 2016
Patent Number:
9508805
A termination structure for a semiconductor power device includes a plurality of termination groups formed in a lightly doped epitaxial layer of a first conductivity type over a heavily doped semiconductor substrate of a second conductivity type. Each termination group includes a trench formed in the lightly doped epitaxial layer of the first conductivity type. All sidewalls of the trench are covered by a plurality of epitaxial layers of alternating conductivity types disposed on two…
High frequency switching MOSFETs with low output capacitance using a depletable P-shield
Granted: November 22, 2016
Patent Number:
9502554
Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an…
Charge reservoir IGBT top structure
Granted: November 22, 2016
Patent Number:
9502547
An IGBT device may be formed from a substrate including a bottom semiconductor layer of a first conductivity and an upper semiconductor layer of a second conductivity type located above the bottom semiconductor layer. Trenches for trench gates are formed in the substrate. Each trench extends vertically into the upper semiconductor layer and is provided with a gate insulator on each side of the trench and is filled with polysilicon. A first conductivity type floating body region is formed…
Nanotube semiconductor devices
Granted: November 22, 2016
Patent Number:
9502503
Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first epitaxial layer and a second epitaxial layer formed on mesas of the semiconductor layer. The thicknesses and doping concentrations of the first and second epitaxial layers and the mesa are selected to achieve charge balance in operation. In another embodiment, the semiconductor body is lightly doped and…
Method and structure for wafer level packaging with large contact area
Granted: November 22, 2016
Patent Number:
9502268
A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the…
Compact duty modulator
Granted: November 8, 2016
Patent Number:
9491014
Switching logic receives an input signal and a frequency divided signal and generates switching signals. A delay modulator receives the switching signals and generates a high output when a first node voltage is greater than a second node voltage and low output otherwise. An XOR gate receives the delay modulator's output and the frequency divided signal and produces a final output that is high when one of them is low and the other high and low otherwise. A duty ratio of the final output…
Flyback converter output current evaluation circuit and evaluation method
Granted: November 8, 2016
Patent Number:
9490712
An output current calculating circuit for a flyback converter operating under CCM and DCM is disclosed. The off current value ION and the blanking current value ILEB flowing through a sensing resistor are calculated using a detection module and are summed together using a current summing unit. A voltage converted from the sum value of the off current value IOFF and the blanking current value ILEB is transmitted through an output stage in a predetermined time ratio of a cycle with the…
Device structure and methods of making high density MOSFETs for load switch and DC-DC applications
Granted: November 1, 2016
Patent Number:
9484453
Aspects of the present disclosure describe a high density trench-based power. The active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. A lightly doped sub-body layer may be formed below a body region between two or more adjacent active device structures of the plurality. The sub-body layer extends from a depth of the upper portion of the gate oxide to a depth of the lower portion of…
Integrating enhancement mode depleted accumulation/inversion channel devices with MOSFETs
Granted: November 1, 2016
Patent Number:
9484452
A plurality of gate trenches is formed into an epitaxial region of a first conductivity type over a semiconductor substrate. One or more contact trenches are formed into the epitaxial region, each between two adjacent gate trenches. One or more source regions of the first conductivity type are formed in a top portion of the epitaxial region between a contact trench and a gate trench. A barrier metal is formed inside each contact trench. Each gate trench is substantially filled with a…
Methods for fabricating anode shorted field stop insulated gate bipolar transistor
Granted: October 25, 2016
Patent Number:
9478646
A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.
Semiconductor package with small gate clip and assembly method
Granted: October 18, 2016
Patent Number:
9472491
A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted…
LED current control
Granted: October 11, 2016
Patent Number:
9468055
Parallel light emitting diode channels may be controlled using a pulsed control signal input characterized by an input duty cycle and one or more current sense input signals. Each of the one or more current sense input signals is indicative of a current through a corresponding load channel of one or more load channels. One or more pulsed channel current control signals are provided to one or more corresponding dimming controls correspondingly coupled to the one or more load channels.…
Active ESD protection circuit
Granted: October 11, 2016
Patent Number:
9466972
A high-voltage gate driver circuit configured to drive a high-side power switch and a low-side power switch includes an active dv/dt triggered ESD protection circuit coupled between a protected node and a power rail node. The active dv/dt triggered ESD protection circuit includes a dv/dt circuit controlling an ESD protection transistor connected between the protected node and the power rail node. The ESD protection transistor is turned on when an ESD event occurs at the protected node to…
Source and body contact structure for trench-DMOS devices using polysilicon
Granted: October 11, 2016
Patent Number:
9466710
A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a dielectric disposed on top of the gate electrode, and a doped polysilicon spacer disposed on the source region and along a sidewall of the dielectric. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow…
Latch-up free vertical TVS diode array structure using trench isolation
Granted: October 4, 2016
Patent Number:
9461031
A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device. The method includes a step of opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of the isolation trenches. The method further includes a…
Forming JFET and LDMOS transistor in monolithic power integrated circuit using deep diffusion regions
Granted: October 4, 2016
Patent Number:
9460926
A power integrated circuit includes a junction field effect transistor (JFET) device formed in a first portion of a semiconductor layer with a gate region being formed using a first body region, and a double-diffused metal-oxide-semiconductor (LDMOS) transistor formed in a second portion of the semiconductor layer with a channel being formed in a second body region. The power integrated circuit includes a first deep diffusion region formed under the first body region and in electrical…
Planar srfet using no additional masks and layout method
Granted: September 27, 2016
Patent Number:
9455249
A semiconductor power device is supported on a semiconductor substrate of a first conductivity type with a bottom layer functioning as a bottom electrode and an epitaxial layer overlying the bottom layer with a same conductivity type as the bottom layer. The semiconductor power device includes a plurality of FET cells and each cell further includes a body region of a second conductivity type extending from a top surface into the epitaxial layer. The body region encompasses a heavy body…
High density trench-based power MOSFETs with self-aligned active contacts and method for making such devices
Granted: September 20, 2016
Patent Number:
9450088
Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to…
