High voltage field balance metal oxide field effect transistor (FBM)
Granted: September 20, 2016
Patent Number:
9450083
A semiconductor device includes a semiconductor substrate of a first conductivity type. A first conductivity type epitaxial layer disposed on a top surface of the substrate includes a surface shielded region above a less heavily doped voltage blocking region. A body region of a second conductivity type opposite the first conductivity type is disposed near a top surface of the surface shielded region. A first conductivity type source region is disposed near the top surface inside the body…
Lateral super junctions with high substrate breakdown and build in avalanche clamp diode
Granted: September 20, 2016
Patent Number:
9450050
This invention discloses configurations and methods to manufacture lateral power device including a super-junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance.
Method for forming lateral super-junction structure
Granted: September 20, 2016
Patent Number:
9450045
A fabrication method to form a lateral superjunction structure in a semiconductor device uses N and P type ion implantations into a base epitaxial layer. In some embodiments, the base epitaxial layer is an intrinsic epitaxial layer or a lightly doped epitaxial layer. The method performs simultaneous N and P type ion implantations into the base epitaxial layer. The epitaxial and implantation processes are repeated successively to form multiple implanted base epitaxial layers on a…
Oxide terminated trench MOSFET with three or four masks
Granted: September 13, 2016
Patent Number:
9443928
An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device.
Floating guard ring for HV interconnect
Granted: September 6, 2016
Patent Number:
9437673
Aspects of the present disclosure describe an integrated circuit comprises a substrate of a first conductivity type semiconductor, a lightly doped semiconductor layer of the first conductivity type semiconductor disposed over the substrate, a driver circuit, an electrically conductive interconnect structure formed over the semiconductor layer and electrically connected to the driver circuit at one end, at least one guard structure formed in the semiconductor layer and under the…
Flip chip semiconductor device
Granted: September 6, 2016
Patent Number:
9437587
A semiconductor device package comprises a lead frame having a die paddle comprising a first chip installation area and a second chip installation area, a recess area formed in the first chip installation area, and multiple metal pillars formed in the recess area, a notch divides the first chip installation area into a transverse base extending transversely and a longitudinal base extending longitudinally, and separates the recess area into a transverse recess part formed in the…
Combined packaged power semiconductor device
Granted: September 6, 2016
Patent Number:
9437530
A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally…
Dual-side exposed semiconductor package with ultra-thin die and manufacturing method thereof
Granted: September 6, 2016
Patent Number:
9437528
A dual-side exposed semiconductor package with ultra-thin die and a manufacturing method are disclosed. A die having a source electrode and a gate electrode at top surface is flipped and attached to a die paddle of a lead frame and then is encapsulated with a first molding compound. The first molding compound and the die are ground to reduce the thickness. A mask is applied atop the lead frame with the back of the flipped die exposed and a metal layer is deposited on the exposed area at…
Power device and preparation method thereof
Granted: August 30, 2016
Patent Number:
9431328
A power semiconductor package and a method of preparation are disclosed. The power semiconductor package includes a pair of first and second die paddles arranged side by side, a first semiconductor chip attached to the first die paddle, a second semiconductor chip attached to the second die paddle, a metal clip electrically connecting a first electrode at the top surface of the first semiconductor chip and a first electrode at the top surface of the second semiconductor chip to a second…
Method of forming SGT MOSFETs with improved termination breakdown voltage
Granted: August 30, 2016
Patent Number:
9431495
A method of manufacturing a trench power MOSFET device with improved UIS performance and a high avalanche breakdown voltage is disclosed. The method includes performing a first etching of the epitaxial layer to form an active trench with an initial depth in an active area of the semiconductor substrate and a termination trench with a desired depth in a termination area of the semiconductor substrate, wherein the initial depth of the active trench is smaller than the desired depth of the…
Method of hybrid packaging a lead frame based multi-chip semiconductor device with multiple interconnecting structures
Granted: August 23, 2016
Patent Number:
9425181
A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first…
Recycle photochemical to reduce cost of material and environmental impact
Granted: August 23, 2016
Patent Number:
9421567
This invention discloses an apparatus for coating a semiconductor wafer in a coating chamber comprising a platform for placing the semiconductor wafer thereon. The apparatus further includes a catch and recycle (C&R) apparatus comprises a rim/ring controllable to move below and surround the platform for receiving and catching a coating material spurned off in coating the semiconductor wafer.
MOSFET with integrated schottky diode
Granted: August 9, 2016
Patent Number:
9412733
Aspects of the present disclosure describe a Schottky structure with two trenches formed in a semiconductor material. The trenches are spaced apart from each other by a mesa. Each trench may have first and second conductive portions lining the first and second sidewalls. The first and second portions of conductive material are electrically isolated from each other in each trench. The Schottky contact may be formed at any location between the outermost conductive portions. The Schottky…
Top exposed semiconductor chip package
Granted: August 9, 2016
Patent Number:
9412684
A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls.
Protection circuit including vertical gallium nitride schottky diode and PN junction diode
Granted: August 2, 2016
Patent Number:
9406661
A circuit includes a vertical conduction gallium nitride-based Schottky diode and a vertical conduction silicon based PN junction diode connected in parallel. The Schottky diode and the PN junction diode are packaged in the same semiconductor package and the PN junction diode does not conduct in response to the Schottky diode being forward biased. In some embodiments, the silicon based PN junction diode has a breakdown voltage lower than a breakdown voltage of the gallium nitride-based…
Switching regulator with adaptive PWM/PFM modulator
Granted: July 26, 2016
Patent Number:
9401637
A switching regulator controller for a buck switching regulator incorporates a multi-mode adaptive modulator configured to automatically select between a first operation mode and a second operation mode as a function of the output voltage being generated. In one embodiment, the switching regulator controller compares the output voltage to a comparator reference voltage and is configured to operate in a selected operation mode based on the output voltage. In this manner, a single…
High density MOSFET array with self-aligned contacts enhancement plug and method
Granted: July 26, 2016
Patent Number:
9401409
A semiconductor substrate comprises epitaxial region, body region and source region; an array of interdigitated active nitride-capped trench gate stacks (ANCTGS) and self-guided contact enhancement plugs (SGCEP) disposed above the semiconductor substrate and partially embedded into the source region, the body region and the epitaxial region forming the trench-gated MOSFET array. Each ANCTGS comprises a stack of a polysilicon trench gate embedded in a gate oxide shell and a silicon…
Termination design by metal strapping guard ring trenches shorted to a body region to shrink termination area
Granted: July 19, 2016
Patent Number:
9397154
This invention discloses a semiconductor power device formed in a semiconductor substrate of a first conductivity type comprises an active cell area and a termination area surrounding the active cell area and disposed near edges of the semiconductor substrate. The termination area includes a plurality of trenches filled with a conductivity material forming a shield electrode and insulated by a dielectric layer along trench sidewalls and trench bottom surface wherein the trenches…
Power semiconductor package device having locking mechanism, and preparation method thereof
Granted: July 19, 2016
Patent Number:
9397029
A power semiconductor package device and a method of preparation the device are disclosed. The package device includes a die paddle, a first pin, a second pin, and a semiconductor chip attached to the die paddle. A first electrode, a second electrode and a third electrode of the semiconductor chip are connected to the first pin, the second pin and the die paddle respectively. A plastic package body covers the semiconductor chip, the die paddle, the first pin and the second pin. The first…
Method for packaging a power device with bottom source electrode
Granted: July 12, 2016
Patent Number:
9391005
A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.
