Lateral super-junction MOSFET device and termination structure
Granted: April 12, 2016
Patent Number:
9312381
A lateral superjunction MOSFET device includes a gate structure, a first column connected to the lateral superjunction structure and a second column disposed in close proximity to the first column. The lateral superjunction MOSFET device includes the first column to receive current from the channel when the MOSFET is turned on and to distribute the channel current to the lateral superjunction structure functioning as the drain drift region. The second column disposed near the first…
MOSFET device with reduced breakdown voltage
Granted: April 12, 2016
Patent Number:
9312336
A semiconductor device includes a drain region, an epitaxial layer overlaying the drain region, and an active region. The active region includes: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; a contact trench extending through the source and at least part of the body; a contact electrode disposed in the contact trench; and an implant disposed at least in part along a contact…
Lateral PNP bipolar transistor with narrow trench emitter
Granted: April 12, 2016
Patent Number:
9312335
A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation…
Power semiconductor device and preparation method thereof
Granted: April 5, 2016
Patent Number:
9305870
A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with…
Dual trench-gate IGBT structure
Granted: March 22, 2016
Patent Number:
9293559
Aspects of the present disclosure describe an IGBT device including a substrate including a bottom semiconductor layer of a first conductivity type and an upper semiconductor layer of a second conductivity type, at least one first gate formed in a corresponding first trench disposed over the substrate, and a second gate formed in a second trench disposed over the bottom semiconductor layer. The first and second trenches are provided with gate insulators on each side of the trenches and…
Power device and preparation method thereof
Granted: March 22, 2016
Patent Number:
9293397
A power semiconductor package and a method of preparation are disclosed. The power semiconductor package includes a pair of first and second die paddles arranged side by side, a first semiconductor chip attached to the first die paddle, a second semiconductor chip attached to the second die paddle, a metal clip electrically connecting a first electrode at the top surface of the first semiconductor chip and a first electrode at the top surface of the second semiconductor chip to a second…
Vertical DMOS transistor
Granted: March 15, 2016
Patent Number:
9287384
A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially overlapping the body region and insulated from the semiconductor body by a gate dielectric layer; a source diffusion region of a second conductivity type formed in the body region on a first side of the gate electrode; a trench formed in the semiconductor body on a second side, opposite the first side, of the gate electrode, the trench…
Split-gate trench power MOSFET with protected shield oxide
Granted: March 8, 2016
Patent Number:
9281368
A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating…
Trench MOSFET with integrated Schottky barrier diode
Granted: March 8, 2016
Patent Number:
9281416
A Schottky diode includes first and second trenches formed in a semiconductor layer where the first and second trenches are lined with a thin dielectric layer and filled partially with a trench conductor layer with the remaining portion being filled with a first dielectric layer. Well regions are formed spaced-apart in a top portion of the semiconductor layer between the first and second trenches. A Schottky metal layer is formed on a top surface of the semiconductor layer between the…
Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact
Granted: March 8, 2016
Patent Number:
9281394
A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and…
Packaging structure of a semiconductor device
Granted: March 8, 2016
Patent Number:
9281265
A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the…
Method to manufacture short channel trench MOSFET
Granted: February 23, 2016
Patent Number:
9269805
Aspects of the present disclosure describe a trench MOSFET with a channel length that may be controlled by counterdoping the body-drain junction to form a straggle region adjacent to the trenches. The channel length is defined between the straggle region at the bottom and a source region at the top. Both of the straggle region and the source region are of the same conductivity type though they may be different ion species. It is emphasized that this abstract is provided to comply with…
Embedded package and method thereof
Granted: February 23, 2016
Patent Number:
9269699
The present invention discloses a new embedded package comprising: a pre-mold lead frame with a plurality of chips attached thereon, where the molding material fills the voids of the lead frame, so that the lead frame is entirely solid; a plurality of pins arranged around the lead frame; a metal clip attached on and electrically connecting the chips together; first laminate layer which covers the chips, the lead frame, a metal clip and pins; conductive plug and extension formed to…
OLED power driver circuit
Granted: February 16, 2016
Patent Number:
9265121
An efficient, cost effective power driver for OLED panels is configured with a small BOM without compromising the display quality. The power driver adopts only one Inverting Buck-Boost Converter (IBBC) to regulate the necessary output voltage for the OLED panel load. The output voltage to drive the OLED panel load is supplied by the IBBC and the positive input of the OLED panel is tied into the input power supply of VIN directly without any switch. A DC-DC converter is provided to…
Multi-die semiconductor package
Granted: February 9, 2016
Patent Number:
9257375
A multi-die package has a plurality of leads and first and second semiconductor dies in superimposition and bonded together defining a die stack. The die stack has opposed first and second sides, with each of the first and second semiconductor dies having gate, drain and source regions, and gate, drain and source contacts. The first opposed side has the drain contact of the second semiconductor die, which is in electrical communication with a first set of the plurality of leads. The…
Shielded gate trench MOS with improved source pickup layout
Granted: February 2, 2016
Patent Number:
9252265
A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third…
High frequency switching MOSFETs with low output capacitance using a depletable P-shield
Granted: February 2, 2016
Patent Number:
9252264
Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be…
Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts
Granted: February 2, 2016
Patent Number:
9252239
This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench…
Top-exposed semiconductor package and the manufacturing method
Granted: January 26, 2016
Patent Number:
9245831
A semiconductor package includes a lead frame having a die paddle and a plurality of leads connected to die paddle, where each lead has a lead surface parallel to die paddle and is a continuous extension bending upward from die paddle. A semiconductor chip is mounted on die paddle, where drain metal layer covering a first surface of chip is connected to die paddle, and source metal layer and gate metal layer are located on a second surface opposite to first surface with gate metal layer…
Wafer process for molded chip scale package (MCSP) with thick backside metallization
Granted: January 26, 2016
Patent Number:
9245861
A wafer process for MCSP comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer covering metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer and a thick…
