Method for packaging a power device with bottom source electrode
Granted: July 12, 2016
Patent Number:
9391005
A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.
Input line selector system for battery chargers
Granted: July 5, 2016
Patent Number:
9385530
An input line selector system provided to selectively connect one of two input power lines is configured with a single switch provided in series with each of the input power lines, the connection between the switches being made such that it prevents reverse flow of current in the event that the switches are OFF. A smart, simple and precisely operating automatic line selector is provided to control the operation of the two switches. The line selector system configuration is simple and…
Compact guard ring structure for CMOS integrated circuits
Granted: June 21, 2016
Patent Number:
9373682
An integrated circuit includes a guard ring structure including a guard ring with integrated well taps to reduce the silicon area required for the guard ring structure. In some embodiments, the guard ring structure includes an N-type guard ring surrounded by inner and outer P-type guard rings. The N-type guard ring is formed with interleaving deep N-wells and P-wells that are formed on an N-type buried layer and are electrically shorted together. The inner and outer P-type guard rings…
Flexibly scalable charge balanced vertical semiconductor power devices with a super-junction structure
Granted: June 14, 2016
Patent Number:
9368614
This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of…
Fault tolerant power supply incorporating intelligent load switch to provide uninterrupted power
Granted: June 14, 2016
Patent Number:
9367111
A fault tolerant power supply system includes at least one load switch circuit configured to connect, using a main switch, an input voltage to an output node of the load switch circuit when the load switch circuit is turned on and at least one power channel coupled to the load switch circuit to receive the input voltage. The power channel is configured as a buck converter and includes at least a high-side power switch and a low-side power switch. The fault tolerant power supply system is…
EOS protection for integrated circuits
Granted: May 31, 2016
Patent Number:
9355971
In some embodiment, a fuse structure in a semiconductor device uses a metal fuse element connected to a stacked via fuse link connected to a thin film resistive element. The fuse structure can be incorporated in an integrated circuit for EOS protection. In other embodiments, an integrated EOS/ESD protection circuit includes a current limiting resistor integrated with an ESD protection circuit. In some embodiments, the current limiting resistor is formed in an N-well forming the collector…
Charged balanced devices with shielded gate trench
Granted: May 31, 2016
Patent Number:
9356134
This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as…
Integrating Schottky diode into power MOSFET
Granted: May 31, 2016
Patent Number:
9356132
A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in…
Through silicon via processing method for lateral double-diffused MOSFETs
Granted: May 31, 2016
Patent Number:
9356122
The present invention features methods for forming a field effect transistor on a semiconductor substrate having gate, source and drain regions, with the gate region having a lateral gate channel. A plurality of spaced-apart trenches or through semiconductor vias (TSV) each having an electrically conductive plug formed therein in electrical communication with the gate, source and drain regions are configured to lower the resistance of the bottom source. A contact trench is formed…
Semiconductor device with termination structure for power MOSFET applications
Granted: May 31, 2016
Patent Number:
9356022
A semiconductor device may have an active device region containing a plurality of active devices and a termination structure that surrounds the active device region. The termination structure includes a first conductive region that surrounds the active device region, an insulator region that surrounds the first conductive region, and a second conductive region that surrounds the first conductive region and the insulator region. The active device region and termination structure are…
Vertical semiconductor MOSFET device with double substrate-side multiple electrode connections and encapsulation
Granted: May 31, 2016
Patent Number:
9355953
A semiconductor device with substrate-side exposed device-side electrode (SEDE) is disclosed. The semiconductor device has semiconductor substrate (SCS) with device-side, substrate-side and semiconductor device region (SDR) at device-side. Device-side electrodes (DSE) are formed for device operation. A through substrate trench (TST) is extended through SCS, reaching a DSE turning it into an SEDE. The SEDE can be interconnected via conductive interconnector through TST. A substrate-side…
Nanotube semiconductor devices
Granted: May 24, 2016
Patent Number:
9349796
Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first epitaxial layer and a second epitaxial layer formed on mesas of the semiconductor layer. The thicknesses and doping concentrations of the first and second epitaxial layers and the mesa are selected to achieve charge balance in operation. In another embodiment, the semiconductor body is lightly doped and…
Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier source
Granted: May 10, 2016
Patent Number:
9337329
A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source and that may include a PtSi, ErSi layer and may further be a metal silicide layer having the low barrier height. A top oxide…
Closed cell lateral MOSFET using silicide source and body regions
Granted: May 10, 2016
Patent Number:
9337284
A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in one or more source cells with silicided source and body diffusion regions formed therein. In this manner, the cell pitch of the cellular transistor array is kept small while the ruggedness of the transistor is ensured. In other embodiments, a closed cell lateral MOSFET device is formed using silicided source and body diffusion regions and self-aligned contacts or borderless contacts as the…
Methods and configuration for manufacturing flip chip contact (FCC) power package
Granted: May 10, 2016
Patent Number:
9337132
A power device package for containing, protecting and providing electrical contacts for a power transistor includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an…
Power semiconductor device and the preparation method
Granted: May 10, 2016
Patent Number:
9337131
An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame unit with a staggered structure including an upper section and a lower section. A thin layer is attached on the surface of the lead frame unit having a plurality of contact holes on the upper section and at least one opening on the lower section. A semiconductor chip is attached on the opening on the lower section of the lead frame…
Ultra-thin semiconductor device and preparation method thereof
Granted: May 10, 2016
Patent Number:
9337127
A small and ultra-thin power semiconductor device and a preparation method are disclosed. The device includes a chip mounting unit with a plurality of pads with a plate arranged on top surface of each pad; a semiconductor chip flipped and attached on the chip mounting unit, where the electrodes at the front of the chip are electrically connected to the pads; a plastic packaging body covering the chip mounting units and the chip, where the top surface of the plate and the back surface of…
MCSP power semiconductor devices and preparation methods thereof
Granted: April 19, 2016
Patent Number:
9318424
The present invention discloses the MCSP power semiconductor device and the preparation method thereof. In the present invention method, a metal foil layer is attached to the back of the wafer using a conductive adhesive layer and a composite tape is laminated on the metal foil layer. Thus, individual MCSP power semiconductor devices are separated by cutting the wafer, the conductive adhesive, the metal foil layer and the composite tape along the scribe lines between adjacent…
Method of making a low-Rdson vertical power MOSFET device
Granted: April 19, 2016
Patent Number:
9318603
The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson (drain-source on resistance) of power MOSFETs, and a power MOSFET device made by the method. By forming one or more bottom grooves at the bottom of Si substrate, the on resistance of the power MOSFET device attributed to the substrate is effectively reduced. A matching lead frame base…
Injection control in semiconductor power devices
Granted: April 19, 2016
Patent Number:
9318587
Semiconductor power devices can be formed on substrate structure having a lightly doped semiconductor substrate of a first conductivity type or a second conductivity type opposite to the first conductivity type. A semiconductive first buffer layer of the first conductivity type formed above the substrate. A doping concentration of the first buffer layer is greater than a doping concentration of the substrate. A second buffer layer of the second conductivity type formed above the first…
