Cascode scheme for improved device switching behavior
Granted: November 25, 2014
Patent Number:
8896131
A switching device includes a low voltage normally-off transistor and a control circuit built into a common die. The device includes source, gate and drain electrodes for the transistor and one or more auxiliary electrodes. The drain electrode is on one surface of a die on which the transistor is formed, while each of the remaining electrodes is located on an opposite surface. The one or more auxiliary electrodes provide electrical contact to the control circuit, which is electrically…
Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter
Granted: November 25, 2014
Patent Number:
8896093
A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.
Wafer level chip scale package
Granted: November 18, 2014
Patent Number:
8890296
A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the…
Three-dimensional high voltage gate driver integrated circuit
Granted: November 18, 2014
Patent Number:
8889487
A three-dimensional (3D) gate driver integrated circuit includes a high-side integrated circuit stacked on a low-side integrated circuit where the high-side integrated circuit and the low-side integrated circuit are interconnected using through-silicon vias (TSV). As thus formed, the high-side integrated circuit and the low-side integrated circuit can be formed without termination regions and without buried layers. The 3D gate driver integrated circuit improves ease of high voltage…
Average inductor current control using variable reference voltage
Granted: November 11, 2014
Patent Number:
8884600
A variable reference voltage generation unit used in DC/DC converter includes a sample-hold valley inductor current unit electrically connected to a reference voltage generation unit. The sample-hold valley inductor current unit receives the valley inductor current and converts it into the valley voltage. The reference voltage generation unit receives and converts a current signal two times of a designated current into a voltage signal two times of a designated voltage. The voltage…
Etch depth determination structure
Granted: November 11, 2014
Patent Number:
8884406
A semiconductor device wafer includes a test structure. The test structure includes a layer of material having an angle-shaped test portion disposed on at least a portion of a surface of the semiconductor wafer. A ruler marking on the surface of the semiconductor wafer proximate the test portion is adapted to facilitate measurement of a change in length of the test portion.
Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method
Granted: November 4, 2014
Patent Number:
8878292
This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation…
Flip-chip semiconductor chip packing method
Granted: November 4, 2014
Patent Number:
8877555
Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected.
Semiconductor package and fabrication method thereof
Granted: October 21, 2014
Patent Number:
8865523
A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the…
Method for forming a schottky barrier diode integrated with a trench MOSFET
Granted: October 21, 2014
Patent Number:
8865540
A method for forming a Schottky diode including forming first and second trenches in a semiconductor layer, forming a thin dielectric layer lining sidewalls of the first and second trenches; forming a trench conductor layer in the first and second trenches where the trench conductor layer fills a portion of each of the first and second trenches and being the only one trench conductor layer in the first and second trenches; forming a first dielectric layer in the first and second trenches…
Semiconductor device with substrate-side exposed device-side electrode and method of fabrication
Granted: October 21, 2014
Patent Number:
8866267
A semiconductor device with substrate-side exposed device-side electrode (SEDE) is disclosed. The semiconductor device has semiconductor substrate (SCS) with device-side, substrate-side and semiconductor device region (SDR) at device-side. Device-side electrodes (DSE) are formed for device operation. A through substrate trench (TST) is extended through SCS, reaching a DSE turning it into an SEDE. The SEDE can be interconnected via conductive interconnector through TST. A substrate-side…
Symmetric blocking transient voltage suppressor (TVS) using bipolar NPN and PNP transistor base snatch
Granted: October 14, 2014
Patent Number:
8859361
A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors…
Charged balanced devices with shielded gate trench
Granted: October 14, 2014
Patent Number:
8860130
This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as…
High-mobility trench MOSFETs
Granted: October 7, 2014
Patent Number:
8853772
High-mobility vertical trench DMOSFETs and methods for manufacturing are disclosed. A source region, a drain region or a channel region of a high-mobility vertical trench DMOSFET may comprise silicon germanium (SiGe) that increases the mobility of the charge carriers in the channel region. In some embodiments the channel region may be strained to increase channel charge carriers mobility.
Wafer level chip scale package with thick bottom metal exposed and preparation method thereof
Granted: October 7, 2014
Patent Number:
8853003
A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the…
Direct contact in trench with three-mask shield gate process
Granted: September 30, 2014
Patent Number:
8847306
A semiconductor substrate may be etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material separated by an insulator is formed over the first conductive material. A first insulator layer is formed on the trenches. A body layer is formed in the substrate. A source is formed in the body layer. A second insulator layer is formed on the trenches and source. Source and gate contacts are formed through…
Method and apparatus for ultra thin wafer backside processing
Granted: September 30, 2014
Patent Number:
8846532
A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support…
Manufacturing method of a semiconductor package of small footprint with a stack of lead frame die paddle sandwiched between high-side and low-side MOSFET
Granted: September 23, 2014
Patent Number:
8841167
A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A…
Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process
Granted: September 16, 2014
Patent Number:
8835251
A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the…
TVS with low capacitance and forward voltage drop with depleted SCR as steering diode
Granted: September 16, 2014
Patent Number:
8835977
A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further…
