Multi-port power delivery system and related control method
Granted: January 11, 2022
Patent Number:
11221658
A multi-port power delivery system includes a first universal serial bus (USB) port, a second USB port, a first power conversion unit, a second power conversion unit, a power delivery control circuit and a switch circuit. The first USB port is configured to output power delivered to a first power path. The second USB port is configured to output power delivered to a second power path. The first power conversion unit has a first output terminal coupled to the first power path. The second…
Port controller power path short detection
Granted: December 21, 2021
Patent Number:
11205894
A multi-port system and method implements fault detection using a resistor connected to each port controller where the resistors of at least two port controllers are connected together in parallel. Each port controller supplies a predetermined current to the associated resistor and senses the resistor voltage of the parallelly connected resistors to detect for a fault condition. A failure condition is indicated when the resistor voltage is outside of a given threshold window. In this…
Slope compensation for current mode control modulator
Granted: December 7, 2021
Patent Number:
11196409
A ramp signal generator generates a slope compensated ramp signal with optimal slope compensation for a current mode control modulator. In some embodiments, the ramp signal generator generates a ramp signal for the current control loop having a first ramp portion with slope compensation and a second ramp portion that matches the expected current mode signal. In some embodiments, the ramp signal generator is implemented using a switched capacitor circuit with charge scaling to generate…
Isolated coupling structure
Granted: November 9, 2021
Patent Number:
11170926
An isolation coupling structure for transmitting a feedback signal between a secondary side and a primary side of a voltage conversion device includes a first dielectric layer including a first face and a second face opposite to the first face, a first coupling coil disposed on the first face enclosing to form an inner region; a second coupling coil configured to couple with the first coupling coil. The second coupling coil includes a first coil portion and a second coil portion, where…
High surge transient voltage suppressor
Granted: October 19, 2021
Patent Number:
11152351
A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating individually optimized collector-base and emitter-base junctions with the optimized junctions being spatially distributed. The optimized collector-base and emitter-base junctions both realize…
Pulse transformer
Granted: September 21, 2021
Patent Number:
11127520
A voltage converter comprises a second controller as a power switch of the secondary side of the transformer for comparing a detection voltage representing an output voltage and/or load current with a first reference voltage and generating a control signal, and a coupling element for transmitting the control signal generated by the second controller to the first controller on the primary side of the transformer enabling the first controller to generate a first pulse signal driving the…
Method of making reverse conducting insulated gate bipolar transistor
Granted: August 24, 2021
Patent Number:
11101137
A process is applied to develop a plurality of reverse conducting insulated gate bipolar transistors (RCIGBTs). The process comprises the steps of providing a wafer, applying a first grinding process, patterning a mask, applying an etching process, removing the mask, implanting N++ type dopant, applying a second grinding process forming a TAIKO ring, implanting P+ type dopant, annealing and depositing TiNiAg or TiNiVAg, removing the TAIKO ring, attaching a tape, and applying a…
Digitally programmable, fully differential error amplifier
Granted: August 24, 2021
Patent Number:
11099589
An error amplifier circuit receives first and second input signals and provides an error amplifier output signal indicative of the difference between the first and second input signals. The error amplifier circuit implements a proportional-integrator-differentiator (PID) circuit having a differential input signal path and including a proportional amplifier circuit, an integrator amplifier circuit, and a differentiator amplifier circuit. The differentiator amplifier circuit receives an AC…
Semiconductor package including low side field-effect transistors and high side field-effect transistors and method of making the same
Granted: August 17, 2021
Patent Number:
11094617
A semiconductor package comprises a lead frame, a first field-effect transistor (FET), a second low side FET, a first high side FET, a second high side FET, a first metal clip, a second metal clip, and a molding encapsulation. The semiconductor package further comprises an optional integrated circuit (IC) controller or an optional inductor. A method for fabricating a semiconductor package. The method comprises the steps of providing a lead frame; attaching a first low side FET, a second…
Integration of HVLDMOS with shared isolation region
Granted: July 20, 2021
Patent Number:
11069804
A power device, comprising, a semiconductor substrate composition having a substrate layer of a first conductivity type, one or more lateral double diffused metal oxide semiconductor (LDMOS) devices formed in the substrate layer. LDMOS structures are integrated in to the isolation region of a high voltage well. Each LDMOS is isolated from a power device substrate area by an isolator structure formed from the substrate layer. Each LDMOS comprises a continuous field plate formed at least…
Semiconductor package and method of making the same
Granted: July 20, 2021
Patent Number:
11069604
A semiconductor package has a plurality of pillars or portions of a plurality of lead strips, a plurality of semiconductor devices, one or two molding encapsulations and a plurality of electrical interconnections. The semiconductor package excludes a wire. The semiconductor package excludes a clip. A method is applied to fabricate semiconductor packages. The method includes providing a removable carrier; forming a plurality of pillars or a plurality of lead strips; attaching a plurality…
Wafer level chip scale package structure and manufacturing method thereof
Granted: July 13, 2021
Patent Number:
11062969
A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing…
Sawtooh electric field drift region structure for planar and trench power semiconductor devices
Granted: June 15, 2021
Patent Number:
11038037
A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column…
Super-junction corner and termination structure with graded sidewalls
Granted: June 15, 2021
Patent Number:
11038022
A superjunction power semiconductor device includes a termination region with superjunction structures having higher breakdown voltage than the breakdown voltage of the active cell region. In one embodiment, the termination region includes superjunction structures having lower column charge as compared to the superjunction structures formed in the active cell region. In other embodiments, a superjunction power semiconductor device incorporating superjunction structures with slanted…
Switch circuit with reduced switch node ringing
Granted: June 8, 2021
Patent Number:
11031922
Apparatus and associated methods relate to providing a power stage having an auxiliary power switch coupled to a high-side switch or a low-side switch in parallel and turning on the auxiliary power switch earlier than turning on the high-side switch. In an illustrative example, the auxiliary power switch may be connected with the high-side switch in parallel. The on-resistance of the auxiliary power switch may be greater than the on-resistance of the high-side switch. A gate drive engine…
Semiconductor device incorporating epitaxial layer field stop zone
Granted: June 8, 2021
Patent Number:
11031465
A semiconductor device includes a semiconductor body having a base region incorporating a field stop zone where the base region and the field stop zone are both formed using an epitaxial process. Furthermore, the epitaxial layer field stop zone is formed with an enhanced doping profile to realize improved soft-switching performance for the semiconductor device. In some embodiments, the enhanced doping profile formed in the field stop zone includes varying, non-constant doping levels. In…
Bidirectional switch having back to back field effect transistors
Granted: June 8, 2021
Patent Number:
11031390
A bi-directional semiconductor switching device is formed by forming first and second vertical field effect transistors (FETs) formed in tandem from a semiconductor substrate. A source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side. Gates for both the first and second. FETs are disposed in tandem in a common set of trenches formed a drift region of the semiconductor substrate that is…
Dual-gate trench IGBT with buried floating P-type shield
Granted: May 4, 2021
Patent Number:
10998264
A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate;…
Common source land grid array package
Granted: April 27, 2021
Patent Number:
10991680
A semiconductor package comprises a land grid array substrate, a first VDMOSFET, a second VDMOSFET, and a molding encapsulation. The land grid array substrate comprises a first metal layer, a second metal layer, a third metal layer, a plurality of vias, and a resin. A series of drain pads at a bottom surface of the semiconductor package follow a “drain 1, drain 2, drain 1, and drain 2” pattern. A method for fabricating a semiconductor package. The method comprises the steps of…
USB type-C load switch ESD protection
Granted: April 13, 2021
Patent Number:
10978869
A MOSFET and an electrostatic discharge (ESD) protection device on a common chip includes a MOSFET with a source, a gate, and a drain, and an ESD protection device configured to implement a diode function that is biased to prevent current from flowing through the common chip from the source to the drain.
