METHODS AND APPARATUS FOR IMPLEMENTING PARAMETERIZABLE PROCESSORS AND PERIPHERALS
Granted: June 5, 2008
Application Number:
20080134127
Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a…
Methods and Apparatus for Initiating and Resynchronizing Multi-Cycle SIMD Instructions
Granted: June 5, 2008
Application Number:
20080133892
Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP)…
Methods and Apparatus for a Bit Rake Instruction
Granted: May 22, 2008
Application Number:
20080120494
Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP)…
Method and apparatus for programmably powering down structured application-specific integrated circuits
Granted: May 8, 2008
Application Number:
20080106300
Methods and apparatus for programmably powering down a structured application-specific integrated circuit are provided. At least one of the programmable layers of the structured ASIC that frequently provides some programmability as between or among a small number of alternative functions is used to provide this programmability.
ADJUSTABLE TRANSISTOR BODY BIAS GENERATION CIRCUITRY WITH LATCH-UP PREVENTION
Granted: April 24, 2008
Application Number:
20080094100
An integrated circuit is provided with body bias generation circuitry. The body bias generation circuitry generates a body bias signal that is provided to transistors on a body bias path. The body bias generation circuitry contains an active latch-up prevention circuit that clamps the body bias path at a safe voltage when potential latch-up conditions are detected. The level of body bias signal that is generated by the body bias circuitry is adjustable. The body bias generation circuitry…
Techniques For Providing Calibrated On-Chip Termination Impedance
Granted: March 13, 2008
Application Number:
20080061818
Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to…
Methods and Appartus for Providing Data Transfer Control
Granted: March 6, 2008
Application Number:
20080059663
A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for…
Manifold Array Processor
Granted: February 28, 2008
Application Number:
20080052491
An array processor includes processing elements (00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 22, 23, 30, 31, 32, 33) arranged in clusters (e.g., 44, 46, 48, 50) to form a rectangular array (40). Inter-cluster communication paths (88) are mutually exclusive. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path, thus eliminating half the wiring required for the path. The length of the…
ERROR DETECTION ON PROGRAMMABLE LOGIC RESOURCES
Granted: February 28, 2008
Application Number:
20080052569
Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in…
Clock data recovery circuitry associated with programmable logic device circuitry
Granted: February 7, 2008
Application Number:
20080031385
A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low…
Economical, scalable transceiver jitter test
Granted: January 17, 2008
Application Number:
20080013609
Any number of transceiver channels is tested for jitter generation/tolerance simultaneously. Tested channels use a serial loopback path to connect a transceiver transmit channel to a transceiver receiver channel. Both the transmitter and receiver PLLs are connected to a common reference clock. The reference clock is modulated with jitter at a frequency below the bandwidth of the transmitter PLL but above the bandwidth of the receiver PLL. The magnitude of eye closure (in an eye diagram),…
Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller
Granted: January 17, 2008
Application Number:
20080016262
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FET computation on a digital signal…
METHOD FOR PROGRAMMING A MASK-PROGRAMMABLE LOGIC DEVICE AND DEVICE SO PROGRAMMED
Granted: January 3, 2008
Application Number:
20080005716
A user logic design for a mask-programmable logic device (“MPLD”) may be designed on a comparable or compatible user-programmable logic device (“UPLD”) and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD—i.e., differences between the devices—are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible…
DYNAMIC RAM STORAGE TECHNIQUES
Granted: December 13, 2007
Application Number:
20070285979
Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a supply voltage, and charge is not drained directly from the DRAM storage node. Each DRAM cell has a small number of transistors. The DRAM cell can be used to store configuration data on a programmable integrated circuits (IC). Pass gates are used on programmable ICs to drive signals across the…
Read-Side Calibration for Data Interface
Granted: December 6, 2007
Application Number:
20070282555
Circuits, methods and apparatus are provided to reduce skew among signals being received by a data interface. Signal path delays are varied such that data and strobe signals received at a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration circuitry provides skew adjustment of each data signal path by determining one or more delays in each data signal path and strobe signal path based on relative timings of test…
SOFT ERROR LOCATION AND SENSITIVITY DETECTION FOR PROGRAMMABLE DEVICES
Granted: December 6, 2007
Application Number:
20070283193
Circuits, methods, and apparatus that detect whether a soft error that occurs in stored configuration data is a false positive that can be ignored such that reloading configuration data or other remedial measures are not unnecessarily performed. One example provides an integrated circuit including an error detection circuit and a sensitivity processor. The error detection circuit detects the presence of errors. The sensitivity processor determines whether a detected error can be ignored,…
Write-Side Calibration for Data Interface
Granted: November 29, 2007
Application Number:
20070277071
Circuits, methods and apparatus are provided to reduce skew among signals being provided or transmitted by a data interface. Signal path delays are varied such that signals transmitted by a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration, external circuitry, or design tools can provide skew adjustment of each output channel by determining one or more delays for each output channel path. When aligning multiple…
System and method for design entry and synthesis in programmable logic devices
Granted: November 8, 2007
Application Number:
20070261014
A system and method facilitates the implementation of analog circuitry in electronic programmable devices. A user can specify user measurable parameters for analog features of the circuit, without requiring knowledge of the internal way in which those analog circuit are implemented in the programmable device to achieve desired properties of the analog parameters of interest. The implementation can be performed in different devices which may implement the analog circuit in vastly…
Multitap fractional baud period pre-emphasis for data transmission
Granted: October 18, 2007
Application Number:
20070241795
Pre-emphasis circuitry and methods for signal transmission provide multiple levels of output signal amplification over one or more baud periods after an input signal transition. The multiple, gradually decreasing levels of output signal amplification reduce power consumption and better approximate the desired signal response.
Techniques For Providing Flexible On-Chip Termination Control on Integrated Circuits
Granted: October 11, 2007
Application Number:
20070236247
On-chip termination (OCT)calibration techniques are provided that support input/output (IO) banks on an integrated circuit (IC) using OCT controllers. The OCT controllers calibrate the on-chip termination impedance in the IO banks using a shared parallel bus or separate parallel buses. Multiplexers or select logic in each IO bank select control signals from the OCT controllers in response to select signals. According to some embodiments, each of the IO banks on an IC can receive OCT…
