Systems and methods for configuring a secure computing environment on an integrated circuit
Granted: August 6, 2019
Patent Number:
10372946
A method of dividing a set of components of an integrated circuit is disclosed. Two or more different security labels are assigned to two or more non-overlapping subsets of the set of components. A handoff file is generated based on the non-overlapping subsets and sent to the integrated circuit. The set of components of the integrated circuit is divided according to the non-overlapping subsets based on the system handoff file.
Memory-mapped state bus for integrated circuit
Granted: August 6, 2019
Patent Number:
10372655
Systems and devices are provided for broadcasting a message to addressed logic blocks in lieu of, or in addition to, programming individual status registers of an integrated circuit. One such device may be an integrated circuit that includes a broadcast bus and addressed logic blocks. The broadcast bus may broadcast an addressed message that includes content and a target address. Each of the addressed logic blocks may receive the addressed message from the broadcast bus and use the…
Transceiver parameter solution space visualization to reduce bit error rate
Granted: August 6, 2019
Patent Number:
10372521
Techniques and mechanisms provide a solution space visualization of bit error rates (BER) for combinations of parameter settings of transceivers. Different types of visualizations may be generated.
Programmable logic device with integrated network-on-chip
Granted: July 30, 2019
Patent Number:
10367756
Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.
Network-on-chip with fixed and configurable functions
Granted: July 30, 2019
Patent Number:
10367745
Systems and methods are provided herein for providing an NoC including a configurable array of nodes, where a node of the configurable array of nodes operates in a default operating mode until a replacement operating mode is triggered. For example, when an NoC is unconfigured, a latch bank may be initialized to “clear,” such that no routing decisions are stored. This may enable a default operating mode where routing logic updates the latches' values as needed to implement required…
Safety features for high level design
Granted: July 30, 2019
Patent Number:
10366190
This disclosure relates generally to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. The algorithmic description representation can be specified in a first language and include at least one programming language construct associated with a first safety data type. Compiling the algorithmic description may involve identifying the at least one construct, accessing a first safety data type definition associated with…
Configuring a programmable device using high-level language
Granted: July 30, 2019
Patent Number:
10366189
A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. That compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said…
Systems and methods for operating a flash memory in an integrated circuit
Granted: July 23, 2019
Patent Number:
10359946
A flash memory operating circuit in an integrated circuit includes a buffer memory and a speed mode intellectual property (IP) block. The speed mode IP block is communicatively coupled to the buffer memory. The speed mode IP block performs a flash memory operation on a flash memory in the integrated circuit.
Systems and methods for sharing multiple lock-detect circuitries or multiple phase locked loop blocks
Granted: July 23, 2019
Patent Number:
10361708
Systems and methods related to phase-locked loops circuitry and lock-detect circuitry are provided. Some of the systems and methods allow sharing of lock-detect circuitries between multiple phase-locked loops or other suitable circuitry. Others allow multiple circuitries to select from multiple lock-detect circuitries that may use different lock-detect techniques.
Techniques for determining inductances
Granted: July 23, 2019
Patent Number:
10361554
A circuit system includes a current sensor circuit, a subtractor circuit, a multiplier circuit, and a divider circuit. The current sensor circuit generates a current sense signal that indicates a current through an inductor. The circuit system generates a current value based on the current sense signal. The subtractor circuit determines a voltage difference across the inductor. The multiplier circuit multiplies the voltage difference by a time period that the voltage difference is…
Delaying start of user design execution
Granted: July 16, 2019
Patent Number:
10354706
For an integrated circuit (IC) that is designed to execute user defined operations after initialization, a sequencing circuitry in the IC that delays the start of the user design execution until a set of initial condition has been computed and propagated is provided. The sequencing holds the first group of circuits at an initial state while a second group of circuits computes and propagates a set of initial conditions based at least partly on the initial state of the first group of…
Systems and methods for sleep mode power savings in integrated circuit devices
Granted: July 16, 2019
Patent Number:
10353457
Embodiments of the disclosure relate to systems and methods to reduce power consumption in an integrated circuit (IC) device by controlling various power consuming components of the IC device to a sleep mode when the power consuming components are not in use. The reduction in power consumption by the various power consuming components may reduce power consumption of the IC device in general. In one example, the IC device may include power consuming buffers of data input paths, data…
Apparatus for improving power consumption of communication circuitry and associated methods
Granted: July 9, 2019
Patent Number:
10348311
An integrated circuit (IC) includes communication circuitry, a body bias generator, and a controller. The communication circuitry includes a physical medium attachment (PMA) and a physical coding sublayer (PCS). The body bias generator provides body bias signals to the PMA and PCS. The controller controls the body bias generator such that the body bias signals are controlled to improve a power consumption of the communication circuitry.
Method and apparatus for data detection and event capture
Granted: July 9, 2019
Patent Number:
10346331
One embodiment relates to a data detection and event capture circuit. Data comparator logic receives a monitored data word from a parallel data bus and generates a plurality of pattern detected signals. Any pattern detection logic receives the plurality of pattern detected signals and generates a plurality of any pattern detected signals. Sequence detection logic receives the plurality of pattern detected signals and generates a plurality of sequence detected signals. Another embodiment…
Non-intrusive monitoring and control of integrated circuits
Granted: July 2, 2019
Patent Number:
10339022
A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an…
Method and apparatus for automatic hierarchical design partitioning
Granted: July 2, 2019
Patent Number:
10339243
A method for designing a system on a target device is disclosed. The system is synthesized. The system is partitioned into a plurality of logical sections utilizing information derived from synthesizing the system and prior to performing placement of the system on the target device. Other embodiments are described and claimed.
Methods for incremental circuit design legalization during physical synthesis
Granted: July 2, 2019
Patent Number:
10339241
Configuration data for an integrated circuit may be generated using logic design equipment to implement a logic design on the integrated circuit. The equipment may perform incremental physical synthesis, timing optimization, and legalization operations on the logic design. The equipment may identify timing and legalization constraints and logic blocks that fail the timing constraints, and may determine whether modifying and/or moving the blocks to new locations satisfy the legalization…
Method and apparatus for performing register retiming in the presence of timing analysis exceptions
Granted: July 2, 2019
Patent Number:
10339238
A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.
Dot product based processing elements
Granted: July 2, 2019
Patent Number:
10339201
Systems and methods for calculating a dot product using digital signal processing units that are organized into a dot product processing unit for dot product processing using multipliers and adders of the digital signal processing units.
Integrated circuit with dynamically-adjustable buffer space for serial interface
Granted: July 2, 2019
Patent Number:
10339074
One embodiment relates to an integrated circuit which includes a method of dynamically adjusting a receive buffer in an integrated circuit. A fixed-size buffer circuit of the receive buffer is used to buffer data received by way of a serial interface circuit. The performance of the serial interface circuit are monitored. The receive buffer is dynamically extended based on said performance. Other embodiments, aspects, and features are also disclosed.
