Methods for updating memory maps of a system-on-chip
Granted: June 25, 2019
Patent Number:
10331533
This disclosure relates to techniques for updating a memory map maintained by processing circuitry that is coupled to programmable logic circuitry. One of the techniques may involve detecting reconfiguration of a device component formed on a portion of the programmable logic circuitry using monitoring circuitry. The technique may further include generating a notification event based on the reconfiguration of the device component using the monitoring circuitry. The notification event may…
Differential power analysis resistant encryption and decryption functions
Granted: June 11, 2019
Patent Number:
10320554
Circuits, methods, and systems are provided for securing an integrated circuit device against Differential Power Analysis (DPA) attacks. Plaintext (e.g., configuration data for a programmable device) may be encrypted in an encryption system using a cryptographic algorithm. Ciphertext may be decrypted in a decryption system using the cryptographic algorithm. The encryption and/or decryption systems may obfuscate the plaintext, the ciphertext, and/or the substitution tables used by the…
Systems and methods for data transfer over a shared interface
Granted: June 11, 2019
Patent Number:
10318470
A method for compressing is provided. The method includes compressing, via a processor, a portion of a first data packet to generate a second data packet having a compressed portion. The method includes transmitting the second data packet having the compressed portion via an interface to a co-processor. The processor and the co-processor are communicatively coupled via the interface. The method also includes unpacking, via the co-processor, the compressed portion of the second data…
Fixed-point and floating-point arithmetic operator circuits in specialized processing blocks
Granted: June 11, 2019
Patent Number:
10318241
The present embodiments relate to circuitry that efficiently performs floating-point arithmetic operations and fixed-point arithmetic operations. Such circuitry may be implemented in specialized processing blocks. If desired, the specialized processing blocks may include configurable interconnect circuitry to support a variety of different use modes. For example, the specialized processing block may efficiently perform a fixed-point or floating-point addition operation or a portion…
Method and apparatus for performing symbolic timing analysis with spatial variation
Granted: June 4, 2019
Patent Number:
10311196
A method for designing a system on a target device includes placing the system on the target device. Timing analysis is performed on the placed system to model delays by using a plurality of localized functions that overlap.
Method and apparatus for performing and utilizing source code area annotation
Granted: May 28, 2019
Patent Number:
10303831
A method for designing a system on a target device includes generating a scheduled netlist and a hardware description language (HDL) of the system from a computer language description of the system. An area report is generated prior to HDL compilation, based on estimates from the scheduled netlist, that identifies resources from the target device required to implement portions of the computer language description of the system.
Method and apparatus for performing clock allocation for a system implemented on a programmable device
Granted: May 28, 2019
Patent Number:
10303202
A method for designing a system on a target device includes placing the system on the target device. A netlist retiming is performed on the placed system. A clock allocation and a clock region optimization are performed utilizing information from the placing and the netlist retiming.
Integrated circuit device with embedded programmable logic
Granted: May 21, 2019
Patent Number:
10296474
Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may…
Retiming with fixed power-up states
Granted: May 21, 2019
Patent Number:
10296701
A computer-implemented method includes performing retiming using a circuit design to determine a retimed variation to the circuit design. The circuit design includes a first set of registers with defined power-up states and the variations each comprise a second set of registers that correspond to the first set of registers. The method includes maintaining fixed power-up states for the second set of registers in the variations. The fixed power-up states for the second set of registers are…
Scalable circuitry and method for control insertion
Granted: May 21, 2019
Patent Number:
10296479
The present disclosure provides an innovative circuit structure for control insertion into a multiple-word wide data stream. The control-insertion circuit structure is advantageously scalable as the data width increases. An exemplary implementation of the control-insertion circuit structure includes a multiple-layer shifting circuit. The multiple-layer shifting circuit has some similarities with a barrel shifter. However, unlike a barrel shifter, the multiple-layer shifting circuit moves…
Low-skew channel bonding using phase-measuring FIFO buffer
Granted: May 14, 2019
Patent Number:
10291442
Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission bit-slip circuits slip integer numbers of bits based on the bit-slip control signals. Bypass…
Cross-point programming of pipelined interconnect circuitry
Granted: May 14, 2019
Patent Number:
10289585
An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in storage nodes of a pipeline element and the identical routing signal bypassing the pipeline element. A programming element may access the storage nodes of the pipeline elements for write operations and, if desired, for read operations. For example, the programming element may perform write operations to initialize the storage nodes to a known state during…
Methods and apparatus for embedding an error correction code in storage circuits
Granted: May 14, 2019
Patent Number:
10289483
A computer-aided design (CAD) tool may identify don't care bits in configuration data. The don't care bits in the configuration data may change polarity without affecting the functionality of the circuit design. The CAD tool may compute an error check code (e.g., parity bits for a two-dimensional parity check) and insert the error check code into the configuration data. As an example, the CAD tool may replace don't care bits in the configuration data with the error code. The…
Overcoming retiming limitations due to initial conditions conflicts
Granted: May 7, 2019
Patent Number:
10282508
In one embodiment, a computer-implemented method includes performing retiming using a first circuit design to determine one or more variations to the first circuit design, identifying one or more source registers that are involved in one or more unsuccessful retiming moves due to initial conditions conflicts, and recommending, via a graphical user interface, one or more corrective actions to the one or more source registers to avoid the initial conditions conflicts and improve…
Memory interface circuitry with distributed data reordering capabilities
Granted: May 7, 2019
Patent Number:
10282109
An integrated circuit may include memory interface circuitry for communicating with an external or in-package memory module. The integrated circuit may also include out-of-order (OOO) clients and in-order (IO) clients that issue read and write commands to the memory interface circuitry. The memory interface circuitry may include a memory controller having an OOO command scheduler, a write data buffer, and a simple read data pipeline. The memory interface circuitry may also include a…
Method and apparatus for performing incremental compilation using structural netlist comparison
Granted: April 30, 2019
Patent Number:
10275557
A method for designing a system on a target device includes identifying portions in the system to preserve based on comparing structural characteristics of the system with another system. Design results from the another system are reused for portions in the system that are preserved.
Apparatus for configurable interface and associated methods
Granted: April 23, 2019
Patent Number:
10270447
An field programmable gate array (FPGA) includes a circuit implemented using the FPGA fabric. The FPGA further includes another circuit implemented as hardened circuitry. The FPGA also includes a configurable interface circuit that is adapted to couple together the two circuits.
Hybrid architecture for signal processing and signal processing accelerator
Granted: April 23, 2019
Patent Number:
10268605
Systems and methods for configuring a SPA are disclosed. The SPA comprises a plurality of input ports, a plurality of data memory units, signal processing circuitry, and an enable block including at least two counters. Each counter determines an amount of unprocessed data that is stored in a respective one of the plurality of data memory units, and the enable block is configured to disable the signal processing circuitry until a predetermined amount of data is received over the input…
Memory controller architecture with improved memory scheduling efficiency
Granted: April 23, 2019
Patent Number:
10268392
Integrated circuits that include memory interface and controller circuitry for communicating with external memory are provided. The memory interface and controller circuitry may include a user logic interface, a memory controller, and a physical layer input-output interface. The user logic interface may be operated in a first clock domain. The memory controller may be operated in a second clock domain. The physical layer interface may be operated in a third clock domain that is an…
Retiming with programmable power-up states
Granted: April 9, 2019
Patent Number:
10255404
A computer-implemented includes performing retiming using a circuit design to determine variation to the circuit design. The circuit design includes a first set of registers with defined power-up states and the variations each comprise a second set of registers that correspond to the first set of registers. The method includes computing and maintaining programmable power-up states for the second set of registers in the variations. The programmable power-up states computed for the second…
