Method and apparatus for performing register retiming by utilizing native timing-driven constraints
Granted: September 17, 2019
Patent Number:
10417374
A method for designing a system on a target device includes synthesizing the system. The system is placed on the target device. The system is routed on the target device. Register retiming is performed on the system by applying timing analysis constraints, retiming constraints, bound constraints, and ordering constraints when solving for retiming labels that represent a number and direction of register movement along a path between nodes in the system, and arrival times on all nodes in…
Method and apparatus for deriving signal activities for power analysis and optimization
Granted: September 17, 2019
Patent Number:
10417362
A method for processing signals in a system includes deriving a signal activity for a signal from a timing requirement assignment for the signal.
Methods and apparatus for high-speed serial interface link assist
Granted: September 17, 2019
Patent Number:
10417169
The present disclosure provides a link assist capability that may be added to a compiled design that includes a transceiver. The transceiver with the link assist capability may be dynamically reconfigured to operate in a link assist mode, which is a diagnostic and test mode. The link assist mode may interact with a HSSI link partner, or a design software tool, or a user-defined program. The link assist mode may also facilitate remote debugging. One embodiment relates to an apparatus for…
Pipelined cascaded digital signal processing structures and methods
Granted: September 17, 2019
Patent Number:
10417004
Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a…
Apparatus and method to reduce memory subsystem power dynamically
Granted: September 17, 2019
Patent Number:
10416910
One embodiment relates to a method of saving power in a memory subsystem. A first procedure is performed to save memory controller power by changing a clock toggle rate, and a second procedure is performed to save memory subsystem power by changing a clock frequency for the memory subsystem. A third procedure is performed to rebound back to full speed. Another embodiment relates to a memory subsystem which includes a memory controller, a memory, and a physical input/output interface. The…
Hierarchical accelerator registry for optimal performance predictability in network function virtualization
Granted: September 10, 2019
Patent Number:
10409626
A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. To help improve performance predictability, a hierarchical accelerator registry may be maintained on the coprocessor and/or on local servers. The accelerator registry may assign…
Multi-function, multi-protocol FIFO for high-speed communication
Granted: September 3, 2019
Patent Number:
10404627
Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.
Initial condition support for partial reconfiguration
Granted: August 27, 2019
Patent Number:
10394990
Devices and methods for initializing one or more registers of a programmable integrated circuit (IC) to store an initial condition value are provided. A first bitstream that programs the region of the IC to supply the initial condition value to the one or more registers is first programmed on the IC. Then, once the registers are initialized with the initial condition value, a second bitstream is subsequently programmed to the region of the IC to supply values associated with a function…
Method and apparatus for relocating design modules while preserving timing closure
Granted: August 27, 2019
Patent Number:
10394997
A method for designing a system on a target device includes generating a solution for the system. A solution for a module of the system identified by a user is preserved. The preserved solution for the module is implemented at a location on the target device identified by the user.
Methods and apparatus for dynamically configuring soft processors on an integrated circuit
Granted: August 27, 2019
Patent Number:
10394991
An offloading engine integrated circuit that includes soft processors may be implemented using an aggregated profiler and a soft processor system generation tool. In particular, the aggregated profiler may generate a suggested configuration for soft processors within the integrated circuit. The soft processor system generation tool may use inputs based on the suggested configuration to generate a configuration bit stream that is used to configure the integrated circuit. Soft processors…
Techniques for testing programmable interconnect resources
Granted: August 27, 2019
Patent Number:
10394981
A programmable integrated circuit includes rows of circuit blocks and up and down driving vertical interconnect resources. Each of the up and down driving vertical interconnect resources comprises a programmable signal path coupled to at least two of the rows of circuit blocks. A defect in any one of the up driving vertical interconnect resources in the programmable integrated circuit causes circuit blocks in a different set of the rows to store incorrect values compared to defects in…
Multichip package with protocol-configurable data paths
Granted: August 27, 2019
Patent Number:
10394737
Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with…
Driver for network timing system
Granted: August 27, 2019
Patent Number:
10394734
Devices and methods of providing drivers for software and hardware systems to avoid additional polling or interrupt mechanisms are provided. An electronic device includes a processor supporting a device driver to perform a data packet receiving operation or data packet transmission operation. The device driver causes the processor to receive one or more data packets to a port of the processor according to a time-synchronization protocol. The device driver polls the DMA feature for a…
Synchronize-able modular physical layer architecture for scalable interface
Granted: August 20, 2019
Patent Number:
10389341
One embodiment relates to an integrated circuit with an array of modular physical layer (PHY) slice circuits that are configured into multiple synchronous groups. Each synchronous group receives a delayed synchronous pulse signal provided by a chain of synchronous delay circuits. Another embodiment relates to an array of modular PHY slice circuits, each of which includes a manager circuit that manages the modular PHY slice circuit, a remap circuit that remaps interconnect redundancy, and…
Incremental register retiming of an integrated circuit design
Granted: August 20, 2019
Patent Number:
10387603
A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The…
Pulse-width modulation voltage identification interface
Granted: August 13, 2019
Patent Number:
10382013
Systems, methods, and devices for voltage identification using a pulse-width modulation signal are provided. Such an integrated circuit device may include an input/output (I/O) interface and voltage identification (VID) circuitry. The VID circuitry may be coupled to the input/output interface. The voltage identification circuitry may generate a voltage identification signal that is output on the input/output interface. The voltage identification signal may include a pulsed signal having…
Variable precision floating-point multiplier
Granted: August 13, 2019
Patent Number:
10379815
Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. A multiplier circuit may include a first carry-propagate adder (CPA), a second carry-propagate adder (CPA), and an associated rounding circuit. The first CPA may be wide enough to handle the required precision of the mantissa. In a bridged mode, the first CPA may borrow an additional bit…
Memory-mapped state bus for integrated circuit
Granted: August 6, 2019
Patent Number:
10372655
Systems and devices are provided for broadcasting a message to addressed logic blocks in lieu of, or in addition to, programming individual status registers of an integrated circuit. One such device may be an integrated circuit that includes a broadcast bus and addressed logic blocks. The broadcast bus may broadcast an addressed message that includes content and a target address. Each of the addressed logic blocks may receive the addressed message from the broadcast bus and use the…
Multi-tier time-synchronization architecture
Granted: August 6, 2019
Patent Number:
10374734
Devices and methods to design and use network interfaces compliant with time-synchronization protocols via a multi-tier architecture are provided. This architecture allows for independent development between circuitry related to the time-synchronization protocols and circuitry responsible for channel access, reducing redundancies in the design process.
Systems and methods for configuring a secure computing environment on an integrated circuit
Granted: August 6, 2019
Patent Number:
10372946
A method of dividing a set of components of an integrated circuit is disclosed. Two or more different security labels are assigned to two or more non-overlapping subsets of the set of components. A handoff file is generated based on the non-overlapping subsets and sent to the integrated circuit. The set of components of the integrated circuit is divided according to the non-overlapping subsets based on the system handoff file.
