Programmable logic device with integrated network-on-chip
Granted: July 30, 2019
Patent Number:
10367756
Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.
Systems and methods for sharing multiple lock-detect circuitries or multiple phase locked loop blocks
Granted: July 23, 2019
Patent Number:
10361708
Systems and methods related to phase-locked loops circuitry and lock-detect circuitry are provided. Some of the systems and methods allow sharing of lock-detect circuitries between multiple phase-locked loops or other suitable circuitry. Others allow multiple circuitries to select from multiple lock-detect circuitries that may use different lock-detect techniques.
Techniques for determining inductances
Granted: July 23, 2019
Patent Number:
10361554
A circuit system includes a current sensor circuit, a subtractor circuit, a multiplier circuit, and a divider circuit. The current sensor circuit generates a current sense signal that indicates a current through an inductor. The circuit system generates a current value based on the current sense signal. The subtractor circuit determines a voltage difference across the inductor. The multiplier circuit multiplies the voltage difference by a time period that the voltage difference is…
Systems and methods for operating a flash memory in an integrated circuit
Granted: July 23, 2019
Patent Number:
10359946
A flash memory operating circuit in an integrated circuit includes a buffer memory and a speed mode intellectual property (IP) block. The speed mode IP block is communicatively coupled to the buffer memory. The speed mode IP block performs a flash memory operation on a flash memory in the integrated circuit.
Delaying start of user design execution
Granted: July 16, 2019
Patent Number:
10354706
For an integrated circuit (IC) that is designed to execute user defined operations after initialization, a sequencing circuitry in the IC that delays the start of the user design execution until a set of initial condition has been computed and propagated is provided. The sequencing holds the first group of circuits at an initial state while a second group of circuits computes and propagates a set of initial conditions based at least partly on the initial state of the first group of…
Systems and methods for sleep mode power savings in integrated circuit devices
Granted: July 16, 2019
Patent Number:
10353457
Embodiments of the disclosure relate to systems and methods to reduce power consumption in an integrated circuit (IC) device by controlling various power consuming components of the IC device to a sleep mode when the power consuming components are not in use. The reduction in power consumption by the various power consuming components may reduce power consumption of the IC device in general. In one example, the IC device may include power consuming buffers of data input paths, data…
Apparatus for improving power consumption of communication circuitry and associated methods
Granted: July 9, 2019
Patent Number:
10348311
An integrated circuit (IC) includes communication circuitry, a body bias generator, and a controller. The communication circuitry includes a physical medium attachment (PMA) and a physical coding sublayer (PCS). The body bias generator provides body bias signals to the PMA and PCS. The controller controls the body bias generator such that the body bias signals are controlled to improve a power consumption of the communication circuitry.
Method and apparatus for data detection and event capture
Granted: July 9, 2019
Patent Number:
10346331
One embodiment relates to a data detection and event capture circuit. Data comparator logic receives a monitored data word from a parallel data bus and generates a plurality of pattern detected signals. Any pattern detection logic receives the plurality of pattern detected signals and generates a plurality of any pattern detected signals. Sequence detection logic receives the plurality of pattern detected signals and generates a plurality of sequence detected signals. Another embodiment…
Method and apparatus for implementing user-guided speculative register retiming in a compilation flow
Granted: July 2, 2019
Patent Number:
10339244
A method for designing a system on a target device includes performing speculative register retiming with speculative changes made to a design of the system after an initial compilation of the design. A strategy is generated for an actual register retiming in response to user specified preferences on the speculative changes.
Method and apparatus for phase-aligned 2X frequency clock generation
Granted: July 2, 2019
Patent Number:
10340904
One embodiment relates to a multiple-channel serializer circuit that includes a plurality of one-channel serializers. A one-channel serializer of the plurality of one-channel serializes includes a local 2× frequency clock generator with a non-divider structure. Other embodiments relate to methods of using a non-divider circuit to generate a local 2× frequency clock signal in a one-channel serializer of a multiple-channel serializer. Another embodiment relates to a local 2× frequency…
Method and apparatus for automatic hierarchical design partitioning
Granted: July 2, 2019
Patent Number:
10339243
A method for designing a system on a target device is disclosed. The system is synthesized. The system is partitioned into a plurality of logical sections utilizing information derived from synthesizing the system and prior to performing placement of the system on the target device. Other embodiments are described and claimed.
Methods for incremental circuit design legalization during physical synthesis
Granted: July 2, 2019
Patent Number:
10339241
Configuration data for an integrated circuit may be generated using logic design equipment to implement a logic design on the integrated circuit. The equipment may perform incremental physical synthesis, timing optimization, and legalization operations on the logic design. The equipment may identify timing and legalization constraints and logic blocks that fail the timing constraints, and may determine whether modifying and/or moving the blocks to new locations satisfy the legalization…
Method and apparatus for performing register retiming in the presence of timing analysis exceptions
Granted: July 2, 2019
Patent Number:
10339238
A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.
Dot product based processing elements
Granted: July 2, 2019
Patent Number:
10339201
Systems and methods for calculating a dot product using digital signal processing units that are organized into a dot product processing unit for dot product processing using multipliers and adders of the digital signal processing units.
Integrated circuit with dynamically-adjustable buffer space for serial interface
Granted: July 2, 2019
Patent Number:
10339074
One embodiment relates to an integrated circuit which includes a method of dynamically adjusting a receive buffer in an integrated circuit. A fixed-size buffer circuit of the receive buffer is used to buffer data received by way of a serial interface circuit. The performance of the serial interface circuit are monitored. The receive buffer is dynamically extended based on said performance. Other embodiments, aspects, and features are also disclosed.
Non-intrusive monitoring and control of integrated circuits
Granted: July 2, 2019
Patent Number:
10339022
A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an…
Methods for updating memory maps of a system-on-chip
Granted: June 25, 2019
Patent Number:
10331533
This disclosure relates to techniques for updating a memory map maintained by processing circuitry that is coupled to programmable logic circuitry. One of the techniques may involve detecting reconfiguration of a device component formed on a portion of the programmable logic circuitry using monitoring circuitry. The technique may further include generating a notification event based on the reconfiguration of the device component using the monitoring circuitry. The notification event may…
Methods for memory interface calibration
Granted: June 25, 2019
Patent Number:
10332612
Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. During calibration, duty cycle distortion in data strobe signals may be corrected by selectively delaying the data strobe rising or falling edges. A data clock signal that is used for generating data signals may also suffer from…
System and method for visualization and analysis of a chip view including multiple circuit design revisions
Granted: June 25, 2019
Patent Number:
10331843
A method includes receiving a first circuit design, deriving circuit design revisions based on the first circuit design, receiving revision information for each of the circuit design revisions that is output as a result of compilation of the circuit design revisions, extracting location information, timing information, or both for resources from the revision information, for each of the circuit design revisions, mapping the resources into a chip view based on the location information,…
Method and apparatus for processing data and performing crosstalk simulation
Granted: June 25, 2019
Patent Number:
10331827
A method for performing simulation includes determining whether a model is available for a channel. A model for the channel is generated using signal attenuation parameters provided by a user in response to determining that the model is unavailable. The model includes crosstalk characteristics from crosstalk parameters provided by the user.
