Memory interface circuitry with distributed data reordering capabilities
Granted: May 7, 2019
Patent Number:
10282109
An integrated circuit may include memory interface circuitry for communicating with an external or in-package memory module. The integrated circuit may also include out-of-order (OOO) clients and in-order (IO) clients that issue read and write commands to the memory interface circuitry. The memory interface circuitry may include a memory controller having an OOO command scheduler, a write data buffer, and a simple read data pipeline. The memory interface circuitry may also include a…
Method and apparatus for performing incremental compilation using structural netlist comparison
Granted: April 30, 2019
Patent Number:
10275557
A method for designing a system on a target device includes identifying portions in the system to preserve based on comparing structural characteristics of the system with another system. Design results from the another system are reused for portions in the system that are preserved.
Apparatus for configurable interface and associated methods
Granted: April 23, 2019
Patent Number:
10270447
An field programmable gate array (FPGA) includes a circuit implemented using the FPGA fabric. The FPGA further includes another circuit implemented as hardened circuitry. The FPGA also includes a configurable interface circuit that is adapted to couple together the two circuits.
Hybrid architecture for signal processing and signal processing accelerator
Granted: April 23, 2019
Patent Number:
10268605
Systems and methods for configuring a SPA are disclosed. The SPA comprises a plurality of input ports, a plurality of data memory units, signal processing circuitry, and an enable block including at least two counters. Each counter determines an amount of unprocessed data that is stored in a respective one of the plurality of data memory units, and the enable block is configured to disable the signal processing circuitry until a predetermined amount of data is received over the input…
Memory controller architecture with improved memory scheduling efficiency
Granted: April 23, 2019
Patent Number:
10268392
Integrated circuits that include memory interface and controller circuitry for communicating with external memory are provided. The memory interface and controller circuitry may include a user logic interface, a memory controller, and a physical layer input-output interface. The user logic interface may be operated in a first clock domain. The memory controller may be operated in a second clock domain. The physical layer interface may be operated in a third clock domain that is an…
Retiming with programmable power-up states
Granted: April 9, 2019
Patent Number:
10255404
A computer-implemented includes performing retiming using a circuit design to determine variation to the circuit design. The circuit design includes a first set of registers with defined power-up states and the variations each comprise a second set of registers that correspond to the first set of registers. The method includes computing and maintaining programmable power-up states for the second set of registers in the variations. The programmable power-up states computed for the second…
Routing-efficient time division multiplexing (TDM) data path circuitry
Granted: April 2, 2019
Patent Number:
10250347
TDM circuitry that includes a rotary multiplexer and a memory circuit is provided. A first rotary multiplexer circuit may receive N-bit wide data in accordance to a time division multiple access (TDMA) scheme. The N-bit wide data includes multiple sets of M-bit wide data. The first rotary multiplexer may rotate these sets of the M-bit wide data. The memory circuit is coupled to the first rotary multiplexer circuit. The memory circuit stores each of rotated set of M-bit wide data. A…
Reset sequencing for reducing noise on a power distribution network
Granted: March 26, 2019
Patent Number:
10242141
A computer-implemented method includes receiving a first circuit design for an integrated circuit device, determining when multiple power-drawing events are to occur at substantially the same time via one or more circuitry components of the integrated circuit device, which would have a disruptive effect on a power distribution network of the integrated circuit device, based on the first circuit design, and generating logic that schedules the more than one event so that the more than one…
Method and apparatus for placing and routing partial reconfiguration modules
Granted: March 26, 2019
Patent Number:
10242146
A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.
Methods for minimizing logic overlap on integrated circuits
Granted: March 26, 2019
Patent Number:
10242144
Configuration data for an integrated circuit may be generated using logic design equipment to implement an optimal design on the integrated circuit. Implementing the optimal design may include placing hardware resources within the integrated circuit to decrease or remove overlaps between corresponding hardware resources. A given hardware resource may be defined as a rectangular region, an adjacent hardware resource may be defined as another rectangular region, and together, they may be…
Multi-channel encryption and authentication
Granted: March 19, 2019
Patent Number:
10237066
A scalable and efficient cryptographic architecture is provided for processing data using deeply-pipelined algorithms and circuitries. The architecture can be implemented as circuitry in a fixed logic device, or can be configured into a programmable integrated circuit device. The same top-level design may be used for different choices of data channels, processing depth, parallelism level, and/or system throughput. An encryption pipeline processing block performs rounds of processing upon…
Memory element write-assist circuitry with dummy bit lines
Granted: March 19, 2019
Patent Number:
10236055
Integrated circuits with memory elements are provided. In particular, a group of random-access memory cells may be coupled to first and second data lines via corresponding access transistors. One of the first and second data lines can be driven to a ground voltage level to write a zero or one into a selected memory cell in the group. A first dummy data line can be formed adjacent to the first data line, whereas a second dummy data line can be formed adjacent to the second data line.…
Emulated multiport memory element circuitry with exclusive-OR based control circuitry
Granted: March 19, 2019
Patent Number:
10236043
Integrated circuits may include memory element circuitry. The memory element circuitry may include multiple dual-port memory elements that are controlled to effectively form a multi-port memory element having multiple read and write ports. A respective bank of dual-port memory elements may be coupled to each write port. Write data may be received concurrently over one or more of the write ports and stored on the banks. Switching circuitry may be coupled between the banks and the read…
Partial reconfiguration debugging using hybrid models
Granted: March 19, 2019
Patent Number:
10235485
Circuitry for the simulation of partial reconfiguration of a logic design for an integrated circuit device using a hybrid model is provided. The circuitry may create a hybrid model by combining structural model netlists of one or more partial reconfiguration partitions of the logic design with a behavioral model of a static partition of the logic design. The hybrid model may undergo partial reconfiguration verification to ensure that undefined signals do not bypass a freeze bridge and…
Circuitry and method for decomposable decoder
Granted: March 12, 2019
Patent Number:
10230399
Decoder circuitry for an input channel having a data rate, where a codeword on the input channel includes a plurality of symbols, includes options to provide a first output channel having that data rate, and a plurality of second output channels having slower data rates. The decoder circuitry includes syndrome calculation circuitry, polynomial calculation circuitry, and search-and-correct circuitry. The syndrome calculation circuitry includes finite-field multipliers for multiplying each…
Apparatus and method for security in an integrated circuit
Granted: March 12, 2019
Patent Number:
10228415
Test circuitry for providing security in an integrated circuit includes a control circuit and a test power-on-reset circuit. The control circuit determines whether the integrated circuit is configured in a non-secure condition, and that generates a control signal in response to the non-secure condition. Accordingly, the test power-on-reset circuit selectively disables a power-on-reset circuit on the integrated circuit in response the control signal during test operations. The test…
Method and apparatus for improving system operation by replacing components for performing division during design compilation
Granted: March 5, 2019
Patent Number:
10223488
A method for designing a system on a target device includes identifying components in a netlist that perform a division operation. The netlist is modified during synthesis to utilize other components to compute a result of the division operation by performing a multiplication operation.
Dual signal protocol input/output (I/O) buffer circuit
Granted: March 5, 2019
Patent Number:
10224911
An integrated circuit (IC) device includes a first input/output (I/O) buffer circuit. The first input/output buffer circuit includes first and second groups of stacked transistors. The first group of stacked transistors transfer signals formatted in accordance with only one signal protocol from the group of signal protocols. The second group of stacked transistors transfers the signals formatted in accordance with more than one signal protocols. In addition, integrated circuit device…
Low frequency variation calibration circuitry
Granted: March 5, 2019
Patent Number:
10224908
An integrated circuit may include path delay calibration circuitry. The calibration circuitry may be configured to calibrate respective delay paths so that data and control signals travelling through the respective delay paths experience proper propagation delays during normal user operation. The calibration circuitry may include a high frequency error calibration circuit, a monitoring circuit, and a calibration processing circuit. The high frequency error calibration circuit may be used…
Dynamic tag allocation for clock reconvergence pessimism removal
Granted: March 5, 2019
Patent Number:
10223493
Electronic design automation tools may perform static timing analysis on an integrated circuit design. An integrated circuit design may have multiple nodes that can be traversed using a breadth-first search. To reduce the run-time of static timing analysis tools, tags recording arrival times associated with non-critical paths may have their consolidated in order to include only the critical timing information in the tag, thereby reducing the amount of data that is carried through to the…
