Method and apparatus for improving system operation by replacing components for performing division during design compilation
Granted: March 5, 2019
Patent Number:
10223488
A method for designing a system on a target device includes identifying components in a netlist that perform a division operation. The netlist is modified during synthesis to utilize other components to compute a result of the division operation by performing a multiplication operation.
Dynamic clock-data phase alignment in a source synchronous interface circuit
Granted: February 26, 2019
Patent Number:
10218360
The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary…
Smart diagnosis of integrated circuits including IP cores with encrypted simulation models
Granted: February 26, 2019
Patent Number:
10216877
The present embodiments relate to methods for simulating the behavior of an IP core that has an encrypted simulation model. The encrypted simulation model of the IP core may include a plurality of probes, which a debug option may activate selectively, if desired. The encrypted simulation model may collect data during a simulation as selected by the activated probes of the plurality of probes. The encrypted simulation model may perform smart diagnosis of the collected data based on a set…
Efficient virtual I/O address translation
Granted: February 26, 2019
Patent Number:
10216533
A method includes using a network interface controller to monitor a transmit ring, wherein the transmit ring comprises a circular ring data structure that stores descriptors, wherein a descriptor describes data and comprises a guest bus address that provides a virtual memory location of the data. The method also includes using the network interface controller to determine that a descriptor has been written to the transmit ring. The method further includes using the network interface…
Methods and apparatus for selectively extracting and loading register states
Granted: February 26, 2019
Patent Number:
10216254
Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit.…
Multi-protocol configurable transceiver including configurable deskew in an integrated circuit
Granted: February 26, 2019
Patent Number:
10216219
A configurable multi-protocol transceiver implemented in an integrated circuit (“IC”) includes configurable deskew circuitry. The transceiver has various configurable deskew settings to facilitate effectively adapting transmit and/or receive communications corresponding to a selected one of a plurality of high-speed communication protocols and/or adapt to different implementations in which a deskew block addresses either just static skew or both static and dynamic skew. Configurable…
Embedded memory blocks with adjustable memory boundaries
Granted: February 19, 2019
Patent Number:
10210298
An integrated circuit for configuring memory block portions is provided. The integrated circuit may include a memory block that is partitioned into first and second memory block portions. The first memory block portion has a first memory type and the second memory block portion has a second memory type that is different than the first memory type. The integrated circuit further includes a control circuit configured to receive configuration data. The configuration data may include memory…
Integrated circuit device with field programmable optical array
Granted: February 19, 2019
Patent Number:
10212498
Systems and methods are provided to improve flexibility of optical signal transmission between integrated circuit devices, and more specifically data utilization circuits. More specifically, the integrated circuit devices may include a data utilization circuit communicatively coupled to a field programmable optical array (FPOA). In some embodiments, the FPOA may convert an electrical signal received from the data utilization to an optical signal, route the optical signal to an optical…
Techniques for power control of circuit blocks
Granted: February 19, 2019
Patent Number:
10211833
An integrated circuit includes a circuit block, a storage circuit that stores a static power gating control signal, a logic gate circuit that receives a dynamic power gating control signal and the static power gating control signal from the storage circuit, and a transistor coupled between the circuit block and a supply node at a supply voltage. A conductive state of the transistor is determined by an output signal of the logic gate circuit. The transistor is turned off to provide power…
Integrated circuits with embedded double-clocked components
Granted: February 19, 2019
Patent Number:
10210919
An integrated circuit that includes different types of embedded functional blocks such as programmable logic blocks, memory blocks, and digital signal processing (DSP) blocks is provided. At least a first portion of the functional blocks on the integrated circuit may operate at a normal data rate using a core clock signal while a second portion of the functional blocks on the integrated circuit may operate at a 2× data rate that is double the normal data rate. To support this type of…
Apparatus and methods for on-die temperature sensing to improve FPGA performance
Granted: February 5, 2019
Patent Number:
10200037
A field programmable gate array (FPGA) includes a temperature sensor array. The FPGA also includes a supply voltage modulation circuit. The supply voltage modulation circuit is coupled to the temperature sensor array.
Systems and methods for extraction of electrical specifications from prelayout simulations
Granted: February 5, 2019
Patent Number:
10198545
Systems and methods for extracting one or more electrical specifications from a prelayout simulation of an integrated circuit design, where the one or more electrical specification are utilized to generate a physical layout of one or more components of an integrated circuit.
Circuitry and methods for implementing Galois-field reduction
Granted: January 29, 2019
Patent Number:
10191720
Galois-field reduction circuitry for reducing a Galois-field expansion value, using an irreducible polynomial, includes a plurality of memories, each for storing a respective value derived from the irreducible polynomial and a respective combination of expansion bit values, wherein expansion bits of the expansion value address the plurality of memories to output one or more of the respective values. The Galois-field reduction circuitry also includes exclusive-OR circuitry for combining…
Lutram dummy read scheme during error detection and correction
Granted: January 29, 2019
Patent Number:
10191661
An integrated circuit device includes a first memory cell that stores data representative of configuration data when operating in a first mode, wherein the first memory cell stores data representative of user-accessible data when operating in a second mode. The integrated circuit device also includes a second memory cell that stores a value indicating whether the first memory cell is operating in the first mode or is operating in the second mode. The integrated circuit device further…
High speed FPGA boot-up through concurrent multi-frame configuration scheme
Granted: January 22, 2019
Patent Number:
10186305
Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address…
Methods and apparatus for performing reed-solomon encoding
Granted: January 15, 2019
Patent Number:
10181864
The present embodiments relate to Reed-Solomon encoding, and to circuitry for performing such encoding, particularly in an integrated circuit. A Reed-Solomon encoder circuit may receive a message with data symbols and compute a partial syndrome vector by multiplying the data symbols with a first matrix. The Reed-Solomon encoder circuit may further compute parity check symbols by solving a system of linear equations that includes the partial syndrome vector and a second matrix. As an…
Efficient integrated circuits configuration data management
Granted: January 15, 2019
Patent Number:
10181002
Circuitry for an efficient configuration data management is presented. The circuitry includes an encoding circuit that compares configuration data of a circuit design with base configuration data of a base circuit design. The encoding circuit compresses a difference between the configuration data and the base configuration data to produce compressed configuration data. The compressed configuration data can be stored in a storage circuit. For a purpose of implementing the circuit design…
Techniques for adjusting latency of a clock signal to affect supply voltage
Granted: January 8, 2019
Patent Number:
10175734
An integrated circuit includes circuit blocks, a clock network coupled to the circuit blocks, and a supply voltage network coupled to the circuit blocks. Each of the circuit blocks comprises at least one clocked circuit that receives a clock signal. The clock network provides the clock signal to the clocked circuits in the circuit blocks. The supply voltage network provides a supply voltage to the circuit blocks. A latency of the clock signal provided through the clock network to at…
Omnibus logic element
Granted: January 8, 2019
Patent Number:
10177766
Logic elements (LE) that can provide a number of features. For example, the LE can provide efficient and flexible use of look up tables (LUTs) and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality to provide various modes of operation that enable the various features of the LE.
Techniques for generating pulse-width modulation data
Granted: January 8, 2019
Patent Number:
10177753
An integrated circuit includes a control circuit, a first-in first-out circuit, and a serializer circuit. The control circuit generates parallel pulse-width modulation data in first parallel pulse-width modulation signals. The first-in first-out circuit stores the parallel pulse-width modulation data indicated by the first parallel pulse-width modulation signals. The first-in first-out circuit outputs the stored parallel pulse-width modulation data in second parallel pulse-width…
