Parallel CRC calculation for multiple packets without requiring a shifter
Granted: January 1, 2019
Patent Number:
10171108
Systems and methods are provided herein for removing the need to account for varying lengths of data packets that are transmitted during a single clock cycle, and to require only one CRC calculation block for handling parallel processing of a stream of data packets received during a clock cycle. Moreover, systems and methods are provided herein for eliminating a need for a shifter, such as a barrel shifter, to process the data packets of a single clock cycle in parallel.
Live migration of hardware accelerated applications
Granted: January 1, 2019
Patent Number:
10169065
Live migration of a hardware accelerated application may be orchestrated by cloud services to transfer the application from a source server to a destination server. The live migration may be triggered by probe circuitry that monitors quality of service metrics for migration conditions at the source server. When live migration is initiated by the cloud services, a snapshot of all state information relevant to the application at the source server may be saved to network attached storage…
Adjustable empty threshold limit for a first-in-first-out (FIFO) circuit
Granted: January 1, 2019
Patent Number:
10168989
In one embodiment, transceiver circuitry includes a first-in-first-out (FIFO) circuit and a control logic circuit. The FIFO circuit receives data signals based on a first clock frequency and outputs stored data signals based on a second clock frequency. The stored data signals are transmitted out of the FIFO circuit only in response to a difference between a value of a write pointer of the FIFO circuit and a value of a read pointer of the FIFO circuit exceeding an empty threshold limit…
Voltage regulator with jitter control
Granted: December 25, 2018
Patent Number:
10164517
A voltage regulator package includes a voltage regulator module that outputs a voltage signal of a particular voltage level through an output terminal is provided. The voltage regulator module may be switched on according to a periodic signal having a periodic signal frequency as a variable. The periodic signal frequency may be tuned to reduce impedance, jitter, or noise.
Method and apparatus for performing large scale consensus based clustering
Granted: December 25, 2018
Patent Number:
10162924
A method for designing a system on a target device includes identifying a candidate cluster for a node in the system based on a gain value that quantifies utility for the candidate cluster. The candidate cluster is designated as a final cluster for the node when the candidate cluster has a highest gain value among other candidate clusters for each node in the candidate cluster.
Method and apparatus for improving a design for a system during compilation by performing network replacement
Granted: December 25, 2018
Patent Number:
10162919
A method for designing a system on a target device includes identifying an exclusive-OR (XOR) network in a design for the system that matches an XOR network in a library. The XOR network in the design is replaced with a preferred XOR network in the library.
Integrated circuit retiming with selective modeling of flip-flop secondary signals
Granted: December 25, 2018
Patent Number:
10162918
An integrated circuit design may include registers and combinational logic. Integrated circuit design computing equipment may perform register retiming in the circuit design, whereby registers are moved across one or more portions of the combinational logic. The candidate registers to be retimed may have a different number or different types of secondary signals. In such scenarios, a selective modeling operation may be performed according to a predetermined precedence scheme to remove…
Distributed multi-die protocol application interface
Granted: December 25, 2018
Patent Number:
10162789
Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels.…
Speculative circuit design component graphical user interface
Granted: December 18, 2018
Patent Number:
10157250
In one embodiment, a tangible, non-transitory, computer-readable medium, includes instructions to receive a first circuit design, determine one or more variations of the first circuit design using register retiming with speculative circuit design changes, determine one or more performance improvements of the variations when fed clock signals over the first circuit design, determine one or more tradeoffs of the one or more variations of the first circuit design in comparison to the first…
Constraint based bit-stream compression in hardware for programmable devices
Granted: December 11, 2018
Patent Number:
10152566
A programmable logic device such as an integrated circuit may receive user-defined configuration data from a circuit design system. The user-defined configuration data may include a minimal number of user-defined configuration variables necessary to configure the programmable logic device when combined with hardware-defined configuration variables generated in resolution engines in the programmable logic device based on the user-defined configuration variables. The resolution engines may…
Methods for performing register retiming operations into synchronization regions interposed between circuits associated with different clock domains
Granted: December 11, 2018
Patent Number:
10152565
Circuit design computing equipment may perform register retiming operations to improve the performance of a circuit design after having performed placement and routing operations. For example, the circuit design computing equipment may perform register retiming operations that move registers from a first portion of a circuit design that operates in a first clock domain into a synchronization region that separates the first portion of the circuit design from a second portion of the…
Method and apparatus for designing a system using weighted-cost interconnect synthesis
Granted: December 4, 2018
Patent Number:
10146898
A method for generating a design for a system implemented on a target device includes presenting a user with an interface that allows the user to weight objectives for an interconnect architecture of the design. The interconnect architecture is generated in response to weighted objectives provided by the user.
Adaptive rate-matching first-in first-out (FIFO) system
Granted: December 4, 2018
Patent Number:
10146249
A control system controls First-In First-Out (FIFO) settings of a receiving system. The control system includes a FIFO settings controller that receives a first signal indicative of a first frequency of data received by the receiving system. The FIFO settings controller receives a second signal indicative of a second frequency of a clock that reads the data received by the receiving system. The FIFO settings controller determines a difference (e.g., a parts-per-million (PPM) difference)…
Secure physically unclonable function (PUF) error correction
Granted: November 27, 2018
Patent Number:
10142102
An integrated circuit having a Physically Unclonable Function (PUF) circuit is provided. The PUF circuit may reside as part of a secure subsystem, which also includes a random number generator, a syndrome generator, non-volatile memory, and control circuitry. A predetermined syndrome of a desired PUF response is stored in the non-volatile memory. During normal operation, a current PUF response may be read out from the PUF circuit. The current PUF response may include erroneous bits that…
Pipelined interconnect circuitry with double data rate interconnections
Granted: November 27, 2018
Patent Number:
10141936
An integrated circuit may have pipelined interconnects that are configurable to operate in registered single data rate mode, registered double data rate mode, or in combinational mode. The pipelined interconnect may include routing multiplexers for selecting incoming signals, circuitry for serialization and de-serialization, and memory elements that are configurable to store one or two signals per clock period. Operating the pipeline interconnects in double data rate mode may provide a…
Method and apparatus for performing parallel routing using a multi-threaded routing procedure
Granted: November 27, 2018
Patent Number:
10140411
A method for designing a system to be implemented on a target device, the method including generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing a corresponding net in the bounding box. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
Integrated circuits with specialized processing blocks for performing floating-point fast fourier transforms and complex multiplication
Granted: November 27, 2018
Patent Number:
10140091
Integrated circuits with specialized processing blocks are provided. A specialized processing block may include one real addition stage and one real multiplier stage. The multiplier stage may simultaneously feed its output to the addition stage and directly to an adjacent specialized processing block. The addition stage may also produce sum and difference outputs in parallel. A group of four such specialized processing blocks may be connected in a chain to implement a radix-2 fast…
Methods and apparatus for performing buffer fill level controlled dynamic power scaling
Granted: November 20, 2018
Patent Number:
10136384
Integrated circuits with wireless communications circuitry are provided. The wireless communications circuitry may include an input FIFO, an output FIFO, a processing module interposed between the input and output FIFOs, and dynamic power control circuitry that controls the performance of the processing module. The input and output FIFOs may provide fill level information to the processing module. The dynamic power control circuitry may analyze the current fill level information received…
Flexible physical function and virtual function mapping
Granted: November 20, 2018
Patent Number:
10133594
Techniques and mechanisms provide a flexible mapping for physical functions and virtual functions in an environment including virtual machines.
Selectable reconfiguration for dynamically reconfigurable IP cores
Granted: November 13, 2018
Patent Number:
10127341
Systems and methods for reconfiguration of a hardened intellectual property (IP) block in an integrated circuit (IC) device are provided. Reconfiguration of the hardened IP block in the IC device may transition between functions supported by the hardened IP block. A transition may occur as a pre-configured profile is selected to reconfigure the hardened IP block. Further, configuration data associated with each of the pre-configured profiles of the hardened IP block may be generated and…
