Programmable logic device virtualization
Granted: April 12, 2022
Patent Number:
11303279
A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the…
Multichip package with protocol-configurable data paths
Granted: April 5, 2022
Patent Number:
11294842
Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with…
Methods and apparatus for selectively extracting and loading register states
Granted: March 29, 2022
Patent Number:
11287870
Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit.…
Integrated circuit device with embedded programmable logic
Granted: March 22, 2022
Patent Number:
11281605
Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may…
Hybrid programmable many-core device with on-chip interconnect
Granted: February 22, 2022
Patent Number:
11256656
The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The…
Methods of improving reproductive and respiratory health
Granted: February 8, 2022
Patent Number:
11241464
The present invention encompasses methods of improving reproductive and respiratory health.
Scalable 2.5D interface circuitry
Granted: January 18, 2022
Patent Number:
11226925
A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to…
Scalable 2.5D interface circuitry
Granted: December 7, 2021
Patent Number:
11194757
A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to…
Distributed multi-die protocol application interface
Granted: November 9, 2021
Patent Number:
11169951
Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels.…
Method and apparatus for implementing configurable streaming networks
Granted: November 9, 2021
Patent Number:
11171652
A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to…
Scalable 2.5D interface circuitry
Granted: October 26, 2021
Patent Number:
11157440
A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to…
Programmable device implementing fixed and floating point functionality in a mixed architecture
Granted: October 5, 2021
Patent Number:
11137983
Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point…
Serial memory interface circuitry for programmable integrated circuits
Granted: August 24, 2021
Patent Number:
11101930
A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet…
Method and apparatus for performing fast incremental physical design optimization
Granted: August 17, 2021
Patent Number:
11093672
A method for implementing physical optimizations includes performing physical optimizations on a first reference version of a design, maintaining a computer-readable list of the physical optimizations, and during a subsequent compile for a second version of the design: identifying matching cells, nets, or both between the first reference version of the design and the second version of the design; and restoring at least a subset of the physical optimizations in the second version of the…
Application-based dynamic heterogeneous many-core systems and methods
Granted: August 17, 2021
Patent Number:
11093261
A method for dynamically configuring multiple processors based on needs of applications includes receiving, from an application, an acceleration request message including a task to be accelerated. The method further includes determining a type of the task and searching a database of available accelerators to dynamically select a first accelerator based on the type of the task. The method further includes sending the acceleration request message to a first acceleration interface located…
Method and apparatus for performing different types of convolution operations with the same processing elements
Granted: July 27, 2021
Patent Number:
11074492
A method for implementing a convolutional neural network (CNN) accelerator on a target includes utilizing one or more processing elements to perform convolution. A configuration of the CNN accelerator is modified to change filters implemented by the CNN accelerator and to change formatting of output data. The one or more processing elements are utilized to perform one of deconvolution and backpropagation convolution in response to the change in the filters and formatting of the output…
Channel sizing for inter-kernel communication
Granted: May 25, 2021
Patent Number:
11016742
Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.
Variable precision floating-point multiplier
Granted: May 4, 2021
Patent Number:
10996926
Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. A multiplier circuit may include a first carry-propagate adder (CPA), a second carry-propagate adder (CPA), and an associated rounding circuit. The first CPA may be wide enough to handle the required precision of the mantissa. In a bridged mode, the first CPA may borrow an additional bit…
Methods for optimizing circuit performance via configurable clock skews
Granted: April 6, 2021
Patent Number:
10969820
An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and…
Security RAM block with multiple partitions
Granted: April 6, 2021
Patent Number:
10970409
Circuits, methods, and apparatus for storing application data, keys, authorization codes, or other information in a volatile memory on an FPGA. A field programmable gate array (FPGA) can include multiple memory blocks and partition those blocks among multiple independent reconfigurable regions. Access to the memory blocks can then be restricted so that only authorized regions have access to particular memory partitions. In addition, each partition can store multiple message…
