Methods and apparatus for regulating the supply voltage of an integrated circuit
Granted: June 30, 2020
Patent Number:
10699045
The present embodiments relate to regulating the supply voltage of an integrated circuit. The integrated circuit may implement a circuit design. The circuit design implementation may meet timing constraints with timing margins when operated with the integrated circuit at a nominal supply voltage level. The integrated circuit may further include a voltage identification controller. The voltage identification controller may determine a reduced voltage level based at least on the timing…
Programmable logic device virtualization
Granted: June 16, 2020
Patent Number:
10686449
A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the…
Power gated lookup table circuitry
Granted: June 16, 2020
Patent Number:
10686446
A programmable integrated circuit with lookup table circuitry is provided. The lookup table (LUT) circuitry may be formed using multiplexers. A multiplexer in the lookup table circuitry may be implemented using only tristate inverting circuits. Each tristate inverting circuit may include a first set of n-channel and p-channel transistors that receive a static control bit from a memory element and a second set of n-channel and p-channel transistors that receive true and complementary…
Method and apparatus for implementing a system-level design tool for design planning and architecture exploration
Granted: June 9, 2020
Patent Number:
10678979
A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.
Hybrid architecture for signal processing and signal processing accelerator
Granted: June 9, 2020
Patent Number:
10678715
Systems and methods for configuring a SPA are disclosed. The SPA comprises a plurality of input ports, a plurality of data memory units, signal processing circuitry, and an enable block including at least two counters. Each counter determines an amount of unprocessed data that is stored in a respective one of the plurality of data memory units, and the enable block is configured to disable the signal processing circuitry until a predetermined amount of data is received over the input…
Denormalization in multi-precision floating-point arithmetic circuitry
Granted: June 9, 2020
Patent Number:
10678510
The present embodiments relate to integrated circuits with floating-point arithmetic circuitry that handles normalized and denormalized floating-point numbers. The floating-point arithmetic circuitry may include a normalization circuit and a rounding circuit, and the floating-point arithmetic circuitry may generate a first result in form of a normalized, unrounded floating-point number and a second result in form of a normalized, rounded floating-point number. If desired, the…
Method and apparatus for verifying structural correctness in retimed circuits
Granted: June 2, 2020
Patent Number:
10671790
A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. Whether the retimed design is structurally correct is verified by performing register retiming on the retimed design.
Method and apparatus for performing register retiming in the presence of false path timing analysis exceptions
Granted: June 2, 2020
Patent Number:
10671781
A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.
Techniques for protecting security features of integrated circuits
Granted: May 19, 2020
Patent Number:
10657291
An integrated circuit includes a control circuit and a one-time programmable circuit. The control circuit determines if the one-time programmable circuit is programmed in response to an attempt to access a mode of the integrated circuit after the integrated circuit powers up. The control circuit generates a signal to indicate to a user of the integrated circuit that the mode of the integrated circuit has been previously accessed if the control circuit determines that the one-time…
Configuration via high speed serial link
Granted: May 12, 2020
Patent Number:
10649944
Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.
Integrated circuits with specialized processing blocks for performing floating-point fast fourier transforms and complex multiplication
Granted: May 12, 2020
Patent Number:
10649731
Integrated circuits with specialized processing blocks are provided. A specialized processing block may include one real addition stage and one real multiplier stage. The multiplier stage may simultaneously feed its output to the addition stage and directly to an adjacent specialized processing block. The addition stage may also produce sum and difference outputs in parallel. A group of four such specialized processing blocks may be connected in a chain to implement a radix-2 fast…
Method and apparatus for performing fast incremental physical design optimization
Granted: April 28, 2020
Patent Number:
10635772
A method for designing a system on a target device includes generating a first netlist for a first version of the system after performing synthesis in a first compilation. Optimizations are performed on the first version of the system during placement and routing in the first compilation resulting in a second netlist. A third netlist is generated for a second version of the system after performing synthesis in a second compilation. A hybrid netlist is generated from the first, second,…
Hybrid programmable many-core device with on-chip interconnect
Granted: April 28, 2020
Patent Number:
10635631
The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The…
Multi-rate transceiver circuitry
Granted: April 7, 2020
Patent Number:
10615955
Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may…
Method and apparatus for implementing configurable streaming networks
Granted: April 7, 2020
Patent Number:
10615800
A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to…
Method and apparatus for implementing layers on a convolutional neural network accelerator
Granted: April 7, 2020
Patent Number:
10614354
A method for implementing a convolutional neural network (CNN) accelerator on a target includes utilizing one or more processing elements to implement a standard convolution layer. A configuration of the CNN accelerator is modified to change a data flow between components on the CNN accelerator. The one or more processing elements is utilized to implement a fully connected layer in response to the change in the data flow.
Methods and apparatus for performing product series operations in multiplier accumulator blocks
Granted: April 7, 2020
Patent Number:
10613831
A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of…
Methods and apparatus for performing partial reconfiguration in a pipeline-based network topology
Granted: March 31, 2020
Patent Number:
10606779
A programmable integrated circuit that can support partial reconfiguration is provided. The programmable integrated circuit may include multiple processing nodes that serve as accelerator blocks for an associated host processor that is communicating with the integrated circuit. The processing nodes may be connected in a hybrid shared-pipelined topology. Each pipeline stage in the hybrid architecture may include a bus switch and at least two shared processing nodes connected to the output…
M/A for compiling parallel program having barrier synchronization for programmable hardware
Granted: March 24, 2020
Patent Number:
10599404
A method of compiling program code includes determining if the program code controls a programmable logic device to execute other program code. The program code is a parallel program having a barrier function call for a group of threads. If it is determined that program code is to control the programmable logic device, then the program code is transformed by replacing the barrier function call with control logic inserted into the program code such that the transformed program code…
Programmable integrated circuits with in-operation reconfiguration capability
Granted: March 17, 2020
Patent Number:
10591544
Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use…
