Method and apparatus for implementing configurable streaming networks
Granted: April 7, 2020
Patent Number:
10615800
A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to…
Method and apparatus for implementing layers on a convolutional neural network accelerator
Granted: April 7, 2020
Patent Number:
10614354
A method for implementing a convolutional neural network (CNN) accelerator on a target includes utilizing one or more processing elements to implement a standard convolution layer. A configuration of the CNN accelerator is modified to change a data flow between components on the CNN accelerator. The one or more processing elements is utilized to implement a fully connected layer in response to the change in the data flow.
Methods and apparatus for performing product series operations in multiplier accumulator blocks
Granted: April 7, 2020
Patent Number:
10613831
A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of…
Methods and apparatus for performing partial reconfiguration in a pipeline-based network topology
Granted: March 31, 2020
Patent Number:
10606779
A programmable integrated circuit that can support partial reconfiguration is provided. The programmable integrated circuit may include multiple processing nodes that serve as accelerator blocks for an associated host processor that is communicating with the integrated circuit. The processing nodes may be connected in a hybrid shared-pipelined topology. Each pipeline stage in the hybrid architecture may include a bus switch and at least two shared processing nodes connected to the output…
M/A for compiling parallel program having barrier synchronization for programmable hardware
Granted: March 24, 2020
Patent Number:
10599404
A method of compiling program code includes determining if the program code controls a programmable logic device to execute other program code. The program code is a parallel program having a barrier function call for a group of threads. If it is determined that program code is to control the programmable logic device, then the program code is transformed by replacing the barrier function call with control logic inserted into the program code such that the transformed program code…
Systems and methods for detecting and mitigating of programmable logic device tampering
Granted: March 17, 2020
Patent Number:
10592699
Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected.…
Programmable integrated circuits with in-operation reconfiguration capability
Granted: March 17, 2020
Patent Number:
10591544
Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use…
Method and apparatus for utilizing estimations for register retiming in a design compilation flow
Granted: March 10, 2020
Patent Number:
10586004
A method for designing a system on a target device includes performing one of synthesis, placement, and routing on the system. A designer is presented with a timing analysis of the system after one of the synthesis, placement, and routing, wherein the timing analysis reflects register retiming optimizations predicted to be implemented on the system. One of the synthesis, placement, and routing is modified in response to input provided by the designer after the presenting.
Methods and apparatus for sequencing multiply-accumulate operations
Granted: February 25, 2020
Patent Number:
10572224
An integrated circuit may have specialized processing blocks that are configurable to operate as arithmetic operators that may implement, amongst other functions, multiplication and multiply-accumulation operations in a first mode. In a second mode, a sequencer circuit may provide data signals and control signals to the specialized processing blocks such that the specialized processing block operates as a signal processing device that handles signals in a given sequence. For example, the…
Circuitry and methods for continuous parallel decoder operation
Granted: February 25, 2020
Patent Number:
10574267
Syndrome calculation circuitry for a decoder of codewords having a first number of symbols, where the decoder receives a second number of parallel symbols, and where the first number is not evenly divisible by the second number, includes multipliers equal in number to the second number. Each multiplier multiplies a symbol by a coefficient based on a root of a field of the decoder. The multipliers are divided into a number of groups determined as a function of a modulus of the first…
Variable precision floating-point multiplier
Granted: February 25, 2020
Patent Number:
10572222
Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. A multiplier circuit may include a first carry-propagate adder (CPA), a second carry-propagate adder (CPA), and an associated rounding circuit. The first CPA may be wide enough to handle the required precision of the mantissa. In a bridged mode, the first CPA may borrow an additional bit…
Distributed multi-die protocol application interface
Granted: February 18, 2020
Patent Number:
10565155
Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels.…
Method and apparatus for performing profile guided optimization for high-level synthesis
Granted: February 11, 2020
Patent Number:
10558437
A method for designing a system on a target device includes performing a high-level compilation of a computer program language description of the system to generate a hardware description language (HDL) of the system. The high-level compilation performs optimizations in response to profile data obtained from an earlier compilation of the system.
Memory interface circuitry with distributed data reordering capabilities
Granted: February 4, 2020
Patent Number:
10552052
An integrated circuit may include memory interface circuitry for communicating with an external or in-package memory module. The integrated circuit may also include out-of-order (OOO) clients and in-order (IO) clients that issue read and write commands to the memory interface circuitry. The memory interface circuitry may include a memory controller having an OOO command scheduler, a write data buffer, and a simple read data pipeline. The memory interface circuitry may also include a…
Intellectual property (IP) blocks with customizable configuration status register (CSR) circuitry
Granted: January 28, 2020
Patent Number:
10546087
A method for generating configuration information using a computer aided design (CAD) tool includes a step to receive an intellectual property block. The method also includes a step to receive a configuration and status register (CSR) data file. The configuration and status register data file includes a user selected portion of runtime features from all of the available runtime features of the intellectual property block. The method may also include a step to receive an additional…
Techniques for signal skew compensation
Granted: December 31, 2019
Patent Number:
10523224
An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second…
Programmable circuit having multiple sectors
Granted: December 31, 2019
Patent Number:
10523207
Systems and methods relating to a programmable circuit. The programmable circuit includes multiple sectors. Each sector includes configurable functional blocks, configurable routing wires, configuration bits for storing configurations for the functional blocks and routing wires, and local control circuitry for interfacing with the configuration bits to configure the sector. The programmable circuit may include global control circuitry for interfacing with the local control circuitry to…
State visibility and manipulation in integrated circuits
Granted: December 24, 2019
Patent Number:
10515165
In a first mode, a control circuit can implement a circuit design with storage circuits in an integrated circuit by programming configuration memory bits via configuration resources. The storage circuits can be accessed for read and write operations during execution of the implemented circuit design with the integrated circuit. In a second mode, the control circuit can perform read and write access operations at the storage circuits via configuration resources or via an interface circuit…
Integrated circuits having expandable processor memory
Granted: December 17, 2019
Patent Number:
10509757
Integrated circuits may have programmable logic circuitry and hard-coded circuitry. The hard-coded circuitry may include data circuitry, a processor, and memory. As the hard-coded circuitry has a limited capacity, a portion of the programmable logic circuitry may be configured using configuration data to serve as expanded soft-coded memory for the hard-coded processor. Instructions for controlling settings of the data circuitry may be stored on the hard-coded and soft-coded memory. An…
Integrated circuit package with enhanced cooling structure
Granted: December 10, 2019
Patent Number:
10504819
An integrated circuit package may include an integrated circuit die having first and second circuit regions and a surface. The first circuit region of the integrated circuit package has an operating temperature that is different than that of the second circuit region. A cooling structure is formed on the surface of the integrated circuit die. The cooling structure includes a group of micropipe interconnects arranged to form a cooling channel that allows for the flow of coolant. The…
