Network functions virtualization platforms with function chaining capabilities
Granted: November 26, 2019
Patent Number:
10489178
A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine…
Programmable integrated circuits with multiplexer and register pipelining circuitry
Granted: November 26, 2019
Patent Number:
10489116
An integrated circuit may have specialized processing blocks that are configurable to operate as arithmetic operators that may implement amongst others multiplication, addition, sum-of-product, and multiply-accumulation operations in a first mode. In a second mode, the specialized processing blocks may operate as multiplexers and several specialized processing blocks may be cascaded to implement wider multiplexing functions. In a third mode, the specialized processing blocks may operate…
Techniques for detecting and correcting errors on a ring oscillator
Granted: November 19, 2019
Patent Number:
10483951
A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error…
Memory controller architecture with improved memory scheduling efficiency
Granted: November 19, 2019
Patent Number:
10482934
Integrated circuits that include memory interface and controller circuitry for communicating with external memory are provided. The memory interface and controller circuitry may include a user logic interface, a memory controller, and a physical layer input-output interface. The user logic interface may be operated in a first clock domain. The memory controller may be operated in a second clock domain. The physical layer interface may be operated in third clock domain that is an integer…
Methods and apparatus for controlling interface circuitry
Granted: November 19, 2019
Patent Number:
10482060
A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to…
Apparatus for flexible electronic interfaces and associated methods
Granted: November 12, 2019
Patent Number:
10476505
A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer.
Method and apparatus for performing automatic data compression algorithm selection during high-level compilation
Granted: November 12, 2019
Patent Number:
10474441
A method for performing a high-level compilation of a computer program language (CPL) description of a system to generate a hardware description language (HDL) of the system includes inserting one or more compression/decompression units into the HDL in response to detecting a user inserted term in a kernel definition of an argument in the CPL description to indicate that the argument requires compression.
Programmable device implementing fixed and floating point functionality in a mixed architecture
Granted: November 12, 2019
Patent Number:
10474429
Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point…
Configuring programmable integrated circuit device resources as processors
Granted: October 22, 2019
Patent Number:
10452392
A programmable integrated circuit device includes a plurality of clusters of programmable logic resources. Programmable device interconnect resources allow user-defined interconnection between the clusters of programmable logic resources. A plurality of specialized processing blocks have dedicated arithmetic operators and programmable internal interconnect resources, and having inputs and outputs programmably connectable to the programmable device interconnect resources. A plurality of…
Increasing error rate detection through distribution of read current load
Granted: October 15, 2019
Patent Number:
10446202
Methods and devices for increasing error detection rate while avoiding excessive power distribution network noise are provided. In one method, memory reads of configuration memory of a first group of sectors of a programmable logic device are performed. The memory reads start at a first start time within a first memory read period. The first memory read period includes an amount of time involved to perform one of the memory reads. The method also includes performing memory reads of…
Multi-rate transceiver circuitry
Granted: October 8, 2019
Patent Number:
10439795
Circuitry and methods of operation thereof for video communication are described herein. The circuitry described herein may be programmable circuitry. The circuitry may include a receiver circuit and/or a transmitter circuit and one of the provided techniques includes receiving and/or transmitting video data. The receiver circuit may include a detector circuit that is used to determine the data rate of the received video data stream. The circuitry may further include a transmitter…
Dynamic clock-data phase alignment in a source synchronous interface circuit
Granted: October 8, 2019
Patent Number:
10439615
The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary…
Interface circuitry for parallel computing architecture circuits
Granted: October 8, 2019
Patent Number:
10437743
The present embodiments relate to interface circuitry between a serial interface circuit and an array of processing elements in an integrated circuit. The interface circuitry may include a daisy chain of feeder circuits and a daisy chain of drain circuits. If desired, the interface circuitry may include multiple daisy chains of feeder circuits and/or multiple daisy chains of drain circuits. These multiple daisy chains of feeder circuits and drains circuits may be coupled in parallel,…
Methods and apparatus for reducing power consumption in memory circuitry by controlling precharge duration
Granted: October 1, 2019
Patent Number:
10431269
Integrated circuits with volatile random-access memory cells are provided. A memory cell may be coupled to write bit lines and a read bit line. The write bit line may not be coupled to any precharge circuitry. The read bit line may only be precharged during memory access operations. In one suitable arrangement, the read bit line may be precharge immediately after an address decoding operation and before an evaluation phase. In another suitable arrangement, the read bit line may be…
Method and apparatus for performing register retiming by utilizing native timing-driven constraints
Granted: September 17, 2019
Patent Number:
10417374
A method for designing a system on a target device includes synthesizing the system. The system is placed on the target device. The system is routed on the target device. Register retiming is performed on the system by applying timing analysis constraints, retiming constraints, bound constraints, and ordering constraints when solving for retiming labels that represent a number and direction of register movement along a path between nodes in the system, and arrival times on all nodes in…
Method and apparatus for deriving signal activities for power analysis and optimization
Granted: September 17, 2019
Patent Number:
10417362
A method for processing signals in a system includes deriving a signal activity for a signal from a timing requirement assignment for the signal.
Methods and apparatus for high-speed serial interface link assist
Granted: September 17, 2019
Patent Number:
10417169
The present disclosure provides a link assist capability that may be added to a compiled design that includes a transceiver. The transceiver with the link assist capability may be dynamically reconfigured to operate in a link assist mode, which is a diagnostic and test mode. The link assist mode may interact with a HSSI link partner, or a design software tool, or a user-defined program. The link assist mode may also facilitate remote debugging. One embodiment relates to an apparatus for…
Pipelined cascaded digital signal processing structures and methods
Granted: September 17, 2019
Patent Number:
10417004
Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a…
Apparatus and method to reduce memory subsystem power dynamically
Granted: September 17, 2019
Patent Number:
10416910
One embodiment relates to a method of saving power in a memory subsystem. A first procedure is performed to save memory controller power by changing a clock toggle rate, and a second procedure is performed to save memory subsystem power by changing a clock frequency for the memory subsystem. A third procedure is performed to rebound back to full speed. Another embodiment relates to a memory subsystem which includes a memory controller, a memory, and a physical input/output interface. The…
Hierarchical accelerator registry for optimal performance predictability in network function virtualization
Granted: September 10, 2019
Patent Number:
10409626
A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. To help improve performance predictability, a hierarchical accelerator registry may be maintained on the coprocessor and/or on local servers. The accelerator registry may assign…
