Multi-function, multi-protocol FIFO for high-speed communication
Granted: September 3, 2019
Patent Number:
10404627
Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.
Method and apparatus for relocating design modules while preserving timing closure
Granted: August 27, 2019
Patent Number:
10394997
A method for designing a system on a target device includes generating a solution for the system. A solution for a module of the system identified by a user is preserved. The preserved solution for the module is implemented at a location on the target device identified by the user.
Methods and apparatus for dynamically configuring soft processors on an integrated circuit
Granted: August 27, 2019
Patent Number:
10394991
An offloading engine integrated circuit that includes soft processors may be implemented using an aggregated profiler and a soft processor system generation tool. In particular, the aggregated profiler may generate a suggested configuration for soft processors within the integrated circuit. The soft processor system generation tool may use inputs based on the suggested configuration to generate a configuration bit stream that is used to configure the integrated circuit. Soft processors…
Initial condition support for partial reconfiguration
Granted: August 27, 2019
Patent Number:
10394990
Devices and methods for initializing one or more registers of a programmable integrated circuit (IC) to store an initial condition value are provided. A first bitstream that programs the region of the IC to supply the initial condition value to the one or more registers is first programmed on the IC. Then, once the registers are initialized with the initial condition value, a second bitstream is subsequently programmed to the region of the IC to supply values associated with a function…
Techniques for testing programmable interconnect resources
Granted: August 27, 2019
Patent Number:
10394981
A programmable integrated circuit includes rows of circuit blocks and up and down driving vertical interconnect resources. Each of the up and down driving vertical interconnect resources comprises a programmable signal path coupled to at least two of the rows of circuit blocks. A defect in any one of the up driving vertical interconnect resources in the programmable integrated circuit causes circuit blocks in a different set of the rows to store incorrect values compared to defects in…
Multichip package with protocol-configurable data paths
Granted: August 27, 2019
Patent Number:
10394737
Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with…
Driver for network timing system
Granted: August 27, 2019
Patent Number:
10394734
Devices and methods of providing drivers for software and hardware systems to avoid additional polling or interrupt mechanisms are provided. An electronic device includes a processor supporting a device driver to perform a data packet receiving operation or data packet transmission operation. The device driver causes the processor to receive one or more data packets to a port of the processor according to a time-synchronization protocol. The device driver polls the DMA feature for a…
Synchronize-able modular physical layer architecture for scalable interface
Granted: August 20, 2019
Patent Number:
10389341
One embodiment relates to an integrated circuit with an array of modular physical layer (PHY) slice circuits that are configured into multiple synchronous groups. Each synchronous group receives a delayed synchronous pulse signal provided by a chain of synchronous delay circuits. Another embodiment relates to an array of modular PHY slice circuits, each of which includes a manager circuit that manages the modular PHY slice circuit, a remap circuit that remaps interconnect redundancy, and…
Incremental register retiming of an integrated circuit design
Granted: August 20, 2019
Patent Number:
10387603
A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The…
Pulse-width modulation voltage identification interface
Granted: August 13, 2019
Patent Number:
10382013
Systems, methods, and devices for voltage identification using a pulse-width modulation signal are provided. Such an integrated circuit device may include an input/output (I/O) interface and voltage identification (VID) circuitry. The VID circuitry may be coupled to the input/output interface. The voltage identification circuitry may generate a voltage identification signal that is output on the input/output interface. The voltage identification signal may include a pulsed signal having…
Variable precision floating-point multiplier
Granted: August 13, 2019
Patent Number:
10379815
Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. A multiplier circuit may include a first carry-propagate adder (CPA), a second carry-propagate adder (CPA), and an associated rounding circuit. The first CPA may be wide enough to handle the required precision of the mantissa. In a bridged mode, the first CPA may borrow an additional bit…
Multi-tier time-synchronization architecture
Granted: August 6, 2019
Patent Number:
10374734
Devices and methods to design and use network interfaces compliant with time-synchronization protocols via a multi-tier architecture are provided. This architecture allows for independent development between circuitry related to the time-synchronization protocols and circuitry responsible for channel access, reducing redundancies in the design process.
Circuit structure and method for high-speed forward error correction
Granted: August 6, 2019
Patent Number:
10374636
One embodiment relates a method of receiving data from a multi-lane data link. The data is encoded with an FEC code having a block length. The data is FEC encoded at a bus width which is specified within particular constraints. One constraint is that the FEC encoder bus width in bits is an exact multiple of a number of bits per symbol in the data. Another constraint may be that the FEC code block length is an exact multiple of the FEC encoder bus width. Another constraint may be that the…
Integrated circuit applications using partial reconfiguration
Granted: August 6, 2019
Patent Number:
10374609
Systems and methods for generating and deploying integrated circuit (IC) applications are provided. Partial reconfiguration functionality of an IC may be used to build reconfigurable application platforms that enable application execution on the IC. These apps may include partial reconfiguration bitstreams that allow ease of access to programming without cumbersome compilation via a set of complex tools. The apps may be acquired via a purchasing website or other mechanism, where the…
Systems and methods for configuring a secure computing environment on an integrated circuit
Granted: August 6, 2019
Patent Number:
10372946
A method of dividing a set of components of an integrated circuit is disclosed. Two or more different security labels are assigned to two or more non-overlapping subsets of the set of components. A handoff file is generated based on the non-overlapping subsets and sent to the integrated circuit. The set of components of the integrated circuit is divided according to the non-overlapping subsets based on the system handoff file.
Memory-mapped state bus for integrated circuit
Granted: August 6, 2019
Patent Number:
10372655
Systems and devices are provided for broadcasting a message to addressed logic blocks in lieu of, or in addition to, programming individual status registers of an integrated circuit. One such device may be an integrated circuit that includes a broadcast bus and addressed logic blocks. The broadcast bus may broadcast an addressed message that includes content and a target address. Each of the addressed logic blocks may receive the addressed message from the broadcast bus and use the…
Transceiver parameter solution space visualization to reduce bit error rate
Granted: August 6, 2019
Patent Number:
10372521
Techniques and mechanisms provide a solution space visualization of bit error rates (BER) for combinations of parameter settings of transceivers. Different types of visualizations may be generated.
Configuring a programmable device using high-level language
Granted: July 30, 2019
Patent Number:
10366189
A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. That compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said…
Network-on-chip with fixed and configurable functions
Granted: July 30, 2019
Patent Number:
10367745
Systems and methods are provided herein for providing an NoC including a configurable array of nodes, where a node of the configurable array of nodes operates in a default operating mode until a replacement operating mode is triggered. For example, when an NoC is unconfigured, a latch bank may be initialized to “clear,” such that no routing decisions are stored. This may enable a default operating mode where routing logic updates the latches' values as needed to implement required…
Safety features for high level design
Granted: July 30, 2019
Patent Number:
10366190
This disclosure relates generally to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. The algorithmic description representation can be specified in a first language and include at least one programming language construct associated with a first safety data type. Compiling the algorithmic description may involve identifying the at least one construct, accessing a first safety data type definition associated with…
