MULTI-NODE MEMORY ADDRESS SPACE FOR PCIE DEVICES
Granted: July 6, 2023
Application Number:
20230214345
A device in an interconnect network is provided. The device comprises an end point processor comprising end point memory and an interconnect network link in communication with an interconnect network switch. The device is configured to issue, by the end point processor, a request to send data from the end point memory to other end point memory of another end point processor of another device in the interconnect network and provide, to the interconnect network switch, the request using…
END USER SENSITIVITY PROFILING FOR EFFICIENCY AND PERFORMANCE MANAGEMENT
Granted: July 6, 2023
Application Number:
20230214232
A processing device is provided which comprises memory and a processor, in communication with the memory. The processor is configured to acquire information indicating a sensory perception of a user, determine settings for one or more parameters used to control operation of the device based on the information indicating the sensory perception of the user and control the operation of the device by tuning the one or more parameters according to the determined settings.
FEATURE MANAGEMENT FOR MACHINE LEARNING SYSTEM
Granted: June 29, 2023
Application Number:
20230206113
A technique for processing images is disclosed. The technique includes tracking accesses, by a machine learning system, to individual features of a set of features, to generate an access count for each of the individual features; generating a rank for at least one of the individual features of the set of features based on the access count; and assigning the at least one of the individual features to a level of a memory hierarchy based on the rank.
DRAM SPECIFIC INTERFACE CALIBRATION VIA PROGRAMMABLE TRAINING SEQUENCES
Granted: June 29, 2023
Application Number:
20230207038
Methods and systems are disclosed for training, by a sequencer of a memory interface system, an interface with DRAM. Techniques disclosed comprise scheduling a command sequence, including DRAM commands that are interleaved with one or more CSR commands; executing the scheduled command sequence, wherein the DRAM commands are sent to the DRAM through an internal datapath of the system and the CSR commands are sent to the internal datapath; and training the interface based on exchange of…
VARIABLE TICK FOR DRAM INTERFACE CALIBRATION
Granted: June 29, 2023
Application Number:
20230206973
Methods and systems are disclosed for calibrating, by a memory interface system, an interface with dynamic random-access memory (DRAM) using a dynamically changing training clock. Techniques disclosed comprise receiving a system clock having a clock signal at a first pulse rate. Then, during the training of the interface, techniques disclosed comprise generating a training clock from the clock signal at the first pulse rate, the training clock having a clock signal at a second pulse…
VARIABLE WIDTH BOUNDING VOLUME HIERARCHY NODES
Granted: June 29, 2023
Application Number:
20230206542
A technique for performing ray tracing operations is provided. The technique includes processing small bounding box nodes in a box intersection test circuit to generate intersection test results for the small bounding box nodes; and processing large bounding box nodes in the box intersection test circuit to generate intersection test results for the large bounding box nodes.
COMMON CIRCUITRY FOR TRIANGLE INTERSECTION AND INSTANCE TRANSFORMATION FOR RAY TRACING
Granted: June 29, 2023
Application Number:
20230206541
A technique for performing ray tracing operations is provided. The technique includes traversing through a bounding volume hierarchy to an instance node; performing an instance node transform using common circuitry; traversing to a leaf node of the bounding volume hierarchy; and performing an intersection test for the leaf node using the common circuitry.
BOUNDING VOLUME HIERARCHY BOX NODE COMPRESSION
Granted: June 29, 2023
Application Number:
20230206540
A technique for performing ray tracing operations is provided. The technique includes combining one or more common exponent values of a compressed box node with one or more minimum vertex mantissas of the compressed box node and one or more maximum vertex mantissas of the compressed box node to obtain one or more minimum vertices and one or more maximum vertices; and combining a minimum vertex of the one or more minimum vertices and a maximum vertex of the one or more maximum vertices to…
SYSTEMS AND METHOD FOR GENERATING MORTON CODE
Granted: June 29, 2023
Application Number:
20230206509
Methods and systems are disclosed for encoding a Morton code. Techniques disclosed comprise receiving location vectors associated with primitives, where the primitives are graphical elements spatially located within a three-dimensional scene. Techniques further comprise determining a code pattern comprising a prefix pattern and a base pattern, and, then, coding each of the location vectors according to the code pattern.
DISABLING SELECTED IP
Granted: June 29, 2023
Application Number:
20230206368
A technique for operating a processing device is disclosed. The method includes configuring at least one switch to interconnect one or more selected IP to the processing device, receiving an activation signal associated with the at least one switch based on the one or more selected IP, in response to the activation signal, causing the at least one switch to disable connection to the one or more selected IP, and verifying access to the one or more selected IP is disabled.
MULTI-CHIPLET CLOCK DELAY COMPENSATION
Granted: June 29, 2023
Application Number:
20230205252
Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further…
EMULATING PERFORMANCE OF PRIOR GENERATION PLATFORMS
Granted: June 29, 2023
Application Number:
20230205680
Methods and systems are disclosed for emulating, in a platform, the performance of a target platform. Techniques disclosed include receiving, by the platform, values of system features, associated with a target performance of the target platform; and setting, by the platform, one or more configuration knobs, based on the received values of system features, to match a performance of the platform to the target performance of the target platform.
HARDWARE SUPPORTED SPLIT BARRIER
Granted: June 29, 2023
Application Number:
20230205608
A disclosed technique includes executing, for a first wavefront, a barrier arrival notification instruction, for a first barrier, indicating arrival at a first barrier point; performing, for the first wavefront, work prior to the first barrier point; executing, for the first wavefront, a barrier check instruction; and executing, for the first wavefront, at a control flow path based on a result of the barrier check instruction.
CONTROL FLOW INVARIANT RESOURCE IDENTIFICATION
Granted: June 29, 2023
Application Number:
20230205584
A disclosed technique includes allocating a first set of resource slots for a first execution instance of a pipeline shader program; correlating the first set of resource slots with graphics pipeline passes; and on a second execution instance of the pipeline shader program, assigning resource slots, from the first set of resource slots, to the graphics pipeline passes, based on the correlating.
FORWARD TENSOR AND ACTIVATION SCALING FOR LOWER PRECISION NEURAL NETWORKS
Granted: June 29, 2023
Application Number:
20230205544
A processing device is provided which comprises memory configured to store data and a processor configured to execute a forward activation of the neural network using a low precision floating point (FP) format, scale up values of numbers represented by the low precision FP format and process the scaled up values of the numbers as non-zero values for the numbers. The processor is configured to scale up the values of one or more numbers, via scaling parameters, to a scaled up value equal…
IOMMU COLLOCATED RESOURCE MANAGER
Granted: June 29, 2023
Application Number:
20230205539
Devices, methods and systems for managing resources in a computing device. Information regarding resource usage is captured. A prediction is generated, based on the information, that resource usage by a processor will exceed a threshold during an upcoming time. An operating parameter of the processor is adjusted, based on the prediction. In some implementations, information regarding memory bandwidth is captured. A prediction is generated, based on the information, that a memory region…
DYNAMIC RANDOM-ACCESS MEMORY (DRAM) PHASE TRAINING UPDATE
Granted: June 29, 2023
Application Number:
20230205435
A phase training update circuit operates during a self-refresh cycle of a memory to perform a phase training update on individual bit lanes. The phase training update circuit adjusts a bit lane transmit phase offset forward a designated number of phase steps, transmits a training pattern, and determines a first number of errors in the transmission. It also adjusts the bit lane transmit phase offset backward the designated number of phase steps, transmits the training pattern, and…
REDUCING POWER CONSUMPTION ASSOCIATED WITH FREQUENCY TRANSITIONING IN A MEMORY INTERFACE
Granted: June 29, 2023
Application Number:
20230205433
Methods and systems are disclosed for frequency transitioning in a memory interface system. Techniques disclosed include receiving a signal indicative of a change in operating frequency, into a new frequency, in a processing unit interfacing with memory via the memory interface system; switching the system from a normal mode of operation into a transition mode of operation; updating control and state register (CSR) banks of respective transceivers of the system through a mission bus used…
FLEXIBLE MEMORY SYSTEM
Granted: June 29, 2023
Application Number:
20230205420
A technique for operating a memory system is disclosed. The technique includes performing a first request, by a first memory client, to access data at a first memory address, wherein the first memory address refers to data in a first memory section that is coupled to the first memory client via a direct memory connection; servicing the first request via the direct memory connection; performing a second request, by the first client, to access data at a second memory address, wherein the…
METHOD AND APPARATUS FOR MANAGING POWER STATES
Granted: June 29, 2023
Application Number:
20230205297
A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.
