SYSTEMS AND METHODS FOR IMPROVING RESOURCE UTILIZATION AND SYSTEM PERFORMANCE IN END-TO-END ENCRYPTION
Granted: October 3, 2024
Application Number:
20240333519
The disclosed computing device can include super flow control unit (flit) generation circuitry configured to generate a super flit containing two or more flits having two or more requests embedded therein, wherein the two or more requests have the same destination node identifiers and the super flit has a variable size based on a flit size and a number of existing requests in a source node that target a same destination node. The device can additionally include authentication circuitry…
SPHERE-BASED RAY-CAPSULE INTERSECTOR FOR CURVE RENDERING
Granted: October 3, 2024
Application Number:
20240331266
Devices and methods for rendering curves using ray tracing are provided which include tessellating a curve, representing at least a portion of an object in a scene, into a chain of capsules each comprising two spheres and a connecting cone, generating an acceleration structure comprising the chain of capsules, casting a ray in a space comprising the curve, and performing, for a capsule of the chain of capsules, a closed-form intersection test to render the curve. In a first example, the…
Boot-Up and Memory Testing with Chipset Attached Memory
Granted: October 3, 2024
Application Number:
20240330134
A system that includes at least a system memory, a chipset link, and a chipset attached memory is powered down. A boot-up process is loaded in the chipset attached memory. The boot-up process is performed for the system, via the chipset link, by the chipset attached memory. The boot-up process includes loading one or more memory testing applications. The system memory is tested using the one or more memory testing applications loaded by the chipset attached memory.
Task Allocation with Chipset Attached Memory and Additional Processing Unit
Granted: October 3, 2024
Application Number:
20240330076
Task allocation with chipset attached memory and additional processing unit is described. In accordance with the described techniques, a computing device includes a main system and one or more sub-systems which are coupled to the main system via a chipset link. The main system includes at least a processing unit and a system memory. The one or more sub-systems each include at least a chipset attached processing unit and a chipset attached memory. Contents of the system memory are…
INPUT LOCALITY-ADAPTIVE KERNEL CO-SCHEDULING
Granted: October 3, 2024
Application Number:
20240330045
A technique for scheduling executing items on a highly parallel processing architecture is provided. The technique includes identifying a plurality of execution items that share data, as indicated by having matching commonality metadata; identifying an execution unit for executing the plurality of execution items together; and scheduling the plurality of execution items for execution together on the execution unit.
MEMORY SPRINTING
Granted: October 3, 2024
Application Number:
20240329847
A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.
TESTING MULTI-CYCLE PATHS USING SCAN TEST
Granted: October 3, 2024
Application Number:
20240329135
A disclosed technique includes based on a clock pattern, determining an enable configuration for setting enable signals for one or more multi-cycle paths of a hardware logic network, setting the enable configuration for the one or more multi-cycle paths, and executing testing operations for the hardware logic network with the one or more multi-cycle paths enabled according to the enable configuration.
THERMALLY AWARE STACKING TOPOLOGY
Granted: September 26, 2024
Application Number:
20240321827
A method for circuit die stacking can include providing a first circuit die having a first metal stack, wherein the first circuit die corresponds to a primary thermal source of an integrated circuit including the first circuit die. The method can additionally include providing a second circuit die of the integrated circuit, wherein the second circuit die has a second metal stack and is configured for connection to at least one of a package substrate or an additional die. The method can…
ADVANCED PROCESS IN PROCESS PAIR WITHOUT FUSES
Granted: September 26, 2024
Application Number:
20240324248
A method for die pair partitioning can include providing a circuit die. The method can additionally include providing one or more additional circuit die having one or more fuses positioned therein, wherein the one or more fuses identify the circuit die. The method can also include connecting the one or more additional circuit die to the circuit die. Various other methods, systems, and computer-readable media are also disclosed.
DIE PAIR DEVICE PARTITIONING
Granted: September 26, 2024
Application Number:
20240324247
A method for die pair partitioning can include providing a circuit die that has a metal stack and that includes a majority of logic transistors of an integrated circuit. The method can also include providing one or more additional circuit die that have one or more additional metal stacks of which at least one is connected to the metal stack of the circuit die and a majority of static random access memory and analog devices of the integrated circuit. The method can further include…
BACK END OF LINE OPTIMIZED TO FUNCTION IN A 3D STACK CONFIGURATION
Granted: September 26, 2024
Application Number:
20240321706
A method for implementing shared metal connectivity between 3D stacked circuit dies can include providing a first circuit die having a first metal stack. The method can additionally include providing a second circuit die having a second metal stack, wherein at least one metal layer of the second metal stack is utilized by both the first circuit die and the second circuit die. The method can also include connecting the second metal stack to the first metal stack of the first circuit die.…
BACKSIDE POWER
Granted: September 26, 2024
Application Number:
20240321702
A method for providing backside power can include providing a first circuit die having a first metal stack. The method can also include connecting a second metal stack of a second circuit die to the first metal stack of the first circuit die, wherein a backside power delivery network is located in a passivation layer of at least one of the first circuit die or the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.
TEMPERATURE SENSORS IN DIE PAIR TOPOLOGY
Granted: September 26, 2024
Application Number:
20240321668
A method for die pair partitioning can include providing a first circuit die having a first metal stack. The method can additionally include positioning a second circuit die having a second metal stack in a manner that places a temperature sensor in a transistor layer of the second circuit die in planar proximity to at least one hot spot located in an additional transistor layer of the first circuit die. The method can also include connecting the first metal stack of the first circuit…
Alleviating Interconnect Traffic in a Disaggregated Memory System
Granted: September 26, 2024
Application Number:
20240319911
One or both of read and write accesses to a fabric-attached memory module via a fabric interconnect are monitored. In one or more implementations, offloading of one or more tasks accessing the fabric-attached memory module to a processor of a routing system associated with the fabric-attached memory module is initiated based on the read and write accesses to the fabric-attached memory module. Additionally or alternatively, replicating memory of the fabric-attached memory module to a…
Alleviating Interconnect Traffic in a Disaggregated Memory System
Granted: September 26, 2024
Application Number:
20240319910
One or both of read and write accesses to a fabric-attached memory module via a fabric interconnect are monitored. In one or more implementations, offloading of one or more tasks accessing the fabric-attached memory module to a processor of a routing system associated with the fabric-attached memory module is initiated based on the read and write accesses to the fabric-attached memory module. Additionally or alternatively, replicating memory of the fabric-attached memory module to a…
Duplicating Memory Content with Chipset Attached Memory
Granted: September 26, 2024
Application Number:
20240319903
Duplicating memory content with chipset attached memory is described. In accordance with the described techniques, contents of a system memory are duplicated on a chipset attached memory over a chipset link. Memory requests are serviced using the contents of the system memory and the contents on the chipset attached memory. Servicing the memory requests includes servicing a first portion of a read request using the contents of the system memory and a second, remaining portion of the read…
Multi-Tree Reduction with Execution Skew
Granted: September 19, 2024
Application Number:
20240311182
A device includes a communication scheduler to generate schedule trees for scheduling data communication among a plurality of nodes configured to perform a collective operation using data contributed from the plurality of nodes. The device includes data reduction logic to: identify one or more skewed nodes among the plurality of nodes, perform, according to a first set of schedule trees, a first operation to generate partial results based on data contributed from non-skewed nodes, and…
INTEGRATED CIRCUIT PERFORMANCE ADAPTATION USING WORKLOAD PREDICTIONS
Granted: September 12, 2024
Application Number:
20240302879
Performance adaptation for an integrated circuit includes receiving, by a workload prediction system of a hardware processor, telemetry data for one or more systems of the hardware processor. A workload prediction is determined by processing the telemetry data through a workload prediction model executed by a workload prediction controller of the workload prediction system. A profile is selected, from a plurality of profiles, that matches the workload prediction. The selected profile…
MULTI-CHIPLET CLOCK DELAY COMPENSATION
Granted: September 5, 2024
Application Number:
20240295898
Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further…
EFFICIENT INPUT/OUTPUT MEMORY MANAGEMENT UNIT
Granted: September 5, 2024
Application Number:
20240296128
An input/output memory management unit includes a control logic circuit and a device table entry valid bit array. The control logic circuit provides physical addresses in response to virtual addresses of memory access requests from a plurality of input/output devices. The device table entry valid bit array stores a plurality of valid bits corresponding to different ones of the plurality of input/output devices. The control logic circuit accesses a first valid bit corresponding to a first…
