SYSTEMS AND METHODS FOR COOLING ACCELERATORS HAVING BACK SIDE POWER DELIVERY COMPONENTS
Granted: March 27, 2025
Application Number:
20250107045
A method for cooling accelerators having back side power delivery components can include providing a printed circuit board having a first side that includes an integrated circuit and a first set of one or more power delivery components and a second side that is opposite the first side and that includes a second set of one or more power delivery components. The method can also include positioning a first cooling system to cool the integrated circuit and the first set of one or more power…
TECHNIQUES FOR ELIMINATING VIEW ANGLE LOSS IN IMAGE STABILIZED VIDEO
Granted: March 27, 2025
Application Number:
20250106508
A technique for generating video is provided. The technique includes obtaining a plurality of source frames with a wide-angle camera and a narrow-angle camera; identifying a plurality of central portions and a plurality of peripheral portions of the plurality of source frames based on image stabilization; and combining the plurality of central portions and the plurality of peripheral portions to generate a plurality of resulting frames of an output video.
Access Control Metadata Aware Graph Reordering
Granted: March 27, 2025
Application Number:
20250103650
Graph analytics system are described. In accordance with the described techniques, a graph having vertices that include a first vertex and a second vertex that are associated with access control metadata are received. An updated graph is output based on a merging of the first vertex and the second vertex into a merged vertex of a group of vertices based on the first vertex and the second vertex being associated with access control metadata common to the first vertex and the second vertex…
SYSTEMS AND METHODS FOR DATA COMMUNICATION BUS ADDRESS SHARING
Granted: March 27, 2025
Application Number:
20250103517
A computer-implemented method for data communication bus address sharing can include selecting, by at least one processor, one of two or more peripheral devices sharing an address of a data communication bus. The method can additionally include modulating, by the at least one processor, a duty cycle of a clock signal transmitted over the data communication bus to the two or more peripheral devices, wherein the modulating causes a low period of the clock signal to satisfy a threshold…
SYSTEMS AND METHODS FOR IMPLEMENTING FINE-GRAIN SINGLE ROOT INPUT/OUTPUT (I/O) VIRTUALIZATION (SR-IOV)
Granted: March 27, 2025
Application Number:
20250103371
The disclosed computing device can include host circuitry configured to provide a physical function and guest circuitry configured to provide a virtual function. The host circuitry is configured to dynamically assign request identifiers for accessing at least the host circuitry in a manner that allows the request identifiers to change on a command-to-command basis instead of a time-to-time basis that uses fixed value request identifiers in time slices. Various other methods, systems, and…
SYSTEMS AND METHODS FOR RESYNCHRONIZATION AT EXECUTION TIME
Granted: March 27, 2025
Application Number:
20250103340
A computer-implemented method for resynchronization at execution time can include detecting, by at least one processor and during an execution time of an instruction, a resynchronization. The method can additionally include regenerating, by the at least one processor and in response to the detection, an instruction pointer. The method can also include performing, by the at least one processor and during the execution time of the instruction, the resynchronization by using the regenerated…
TESTING MULTI-CYCLE PATHS BASED ON CLOCK PATTERN
Granted: March 27, 2025
Application Number:
20250102570
A disclosed technique includes based on a clock pattern, determining an enable configuration for setting enable signals for one or more multi-cycle paths of a hardware logic network; controlling a selector to set the enable configuration for the one or more multi-cycle paths; and executing testing operations for the hardware logic network with the one or more multi-cycle paths enabled according to the enable configuration.
DEVICES, SYSTEMS, AND METHODS FOR A PROGRAMMABLE THREE-DIMENSIONAL SEMICONDUCTOR POWER DELIVERY NETWORK
Granted: March 20, 2025
Application Number:
20250096136
A disclosed semiconductor device includes (1) a silicon stack comprising a front-side Back-End-of-Line (BEOL) stack and a back side BEOL stack, the front-side BEOL stack comprising a plurality of signal routes and the back-side BEOL stack comprising a plurality of power delivery routes, and (2) a plurality of auxiliary power paths formed within the front-side BEOL stack and electrically coupled to the plurality of power delivery routes of the back-side BEOL stack via a plurality of…
HYBRID METHODS AND STRUCTURES FOR INCREASING CAPACITANCE DENSITY IN INTEGRATED PASSIVE DEVICES
Granted: March 20, 2025
Application Number:
20250098184
A method for increasing capacitance density within an integrated passive device can include forming a first trench capacitor within a substrate, forming a second trench capacitor within an insulating layer overlying the substrate, and connecting the first and second trench capacitors through connection vias that extend through the insulating layer to form an integrated passive device (IPD) capacitor. A high capacitance density device can include a stacked and co-integrated architecture…
METHODS AND STRUCTURES FOR INCREASING CAPACITANCE DENSITY IN INTEGRATED PASSIVE DEVICES
Granted: March 20, 2025
Application Number:
20250096161
A method for increasing capacitance density within an integrated passive device can include forming a first trench capacitor within a first insulating layer overlying a substrate, forming a second trench capacitor within a second insulating layer overlying the first insulating layer, and connecting the first and second trench capacitors through connection vias that extend through the second insulating layer to form an integrated passive device (IPD) capacitor. A high capacitance density…
SYSTEMS AND METHODS FOR DRIVER CALIBRATION IN DIE-TO-DIE INTERFACES
Granted: March 13, 2025
Application Number:
20250088193
A method for driver calibration in die-to-die interfaces can include calibrating a delay lock loop of a delay line unit cell, by at least one processor, based on drive and load conditions of one or more driver unit cells of a physical layer of a die-to-die interconnect. The method can additionally include generating a clock signal, by the at least one processor, based on the delay lock loop. The method can further include communicating data, by the at least one processor, over the…
DIRECT-CONNECTED MACHINE LEARNING ACCELERATOR
Granted: March 13, 2025
Application Number:
20250086515
Techniques are disclosed for communicating between a machine learning accelerator and one or more processing cores. The techniques include obtaining data at the machine learning accelerator via an input/output die; processing the data at the machine learning accelerator to generate machine learning processing results; and exporting the machine learning processing results via the input/output die, wherein the input/output die is coupled to one or more processor chiplets via one or more…
PERFORMANCE AND MEMORY ACCESS TRACKING AND VISUALIZATION
Granted: March 6, 2025
Application Number:
20250077379
Techniques for performing memory operations are disclosed herein. The techniques include obtaining statistics for operation of a device, the statistics including either or both of performance statistics and memory access statistics; generating a plurality of visualizations of the statistics in one of an overlay mode or a scene annotation mode; and displaying the plurality of visualizations.
Mapping-Aware and Memory Topology-Aware Message Passing Interface Collectives
Granted: March 6, 2025
Application Number:
20250077320
A message passing interface processing system is described. In accordance with message passing logic, a node selects an affinity domain for communication of data associated with a message passing interface and selects a first rank of a first process of the message passing interface assigned to a first partition of the affinity domain as a first partition leader rank and an affinity domain leader rank. The node selects a second rank of a second process of the message passing interface…
Queue Management for Task Graphs
Granted: March 6, 2025
Application Number:
20250077307
In accordance with the described techniques, a command processor processes a fiber graph that includes fibers each having one or more tasks and indicates dependencies between the fibers and between tasks within the fibers. As part of this, the command processor dispatches a task from a fiber for execution by a processing element array based on the fiber being enqueued in a ready queue and the dependencies of the task being resolved. While the task is dispatched and unexecuted by the…
MEMORY CONTROLLER WITH PSEUDO-CHANNEL SUPPORT
Granted: February 20, 2025
Application Number:
20250061071
A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request…
MULTIPLE MEMORY PERFORMANCE STATES USING SYSTEM MEMORY
Granted: February 6, 2025
Application Number:
20250044966
The disclosed device includes a cache that stores sets of settings for memory states, and registers that store a current set of settings for a memory. The device also includes a control circuit that can read, from the cache in response to the memory transitioning to a new memory state, a new set of settings corresponding to the new memory state, and write, to the plurality of registers, the new set of settings. Various other methods, systems, and computer-readable media are also…
MEMORY SELF-REFRESH POWER GATING
Granted: January 30, 2025
Application Number:
20250037750
The disclosed systems and methods include a control circuit for entering a low power state of a memory by preserving a context of the memory's controller and power gating the memory's physical layer. The context can be saved to a non-volatile memory device or by keeping a retention supply voltage to a register of the memory controller. Various other methods, systems, and computer-readable media are also disclosed.
ACTIVE HIBERNATE AND MANAGED MEMORY COOLING IN A NON-UNIFORM MEMORY ACCESS SYSTEM
Granted: January 30, 2025
Application Number:
20250036467
A method of operating a computing system includes storing a memory map identifying a first physical memory address as associated with a high performance memory and identifying a second physical memory address as associated with a low power consumption memory, servicing a first memory access request received from an application by accessing application data at the first physical memory address, in response to a change in one or more operating conditions of the computing system, moving the…
SYSTEMS AND METHODS FOR ABNORMAL POWER CONNECTION DETECTION
Granted: January 23, 2025
Application Number:
20250028010
A computer-implemented method for abnormal power connection detection can include receiving, by at least one processor, a power signal by a power connector and an additional power signal by an additional power connector. The method can additionally include performing, by the at least one processor, one or more measurements of the additional power signal. The method can also include carrying out, by the at least one processor, one or more response procedures based on the one or more…
