Bank-Level Parallelism for Processing in Memory
Granted: March 28, 2024
Application Number:
20240103763
In accordance with the described techniques for bank-level parallelism for processing in memory, a plurality of commands are received for execution by a processing in memory component embedded in a memory. The memory includes a first bank and a second bank. The plurality of commands include a first stream of commands which cause the processing in memory component to perform operations that access the first bank and a second stream of commands which cause the processing in memory…
Memory Control for Data Processing Pipeline Optimization
Granted: March 28, 2024
Application Number:
20240103719
Generating optimization instructions for data processing pipelines is described. A pipeline optimization system computes resource usage information that describes memory and compute usage metrics during execution of each stage of the data processing pipeline. The system additionally generates data storage information that describes how data output by each pipeline stage is utilized by other stages of the pipeline. The pipeline optimization system then generates the optimization…
FRAMEWORK FOR COMPRESSION-AWARE TRAINING OF NEURAL NETWORKS
Granted: March 21, 2024
Application Number:
20240095517
Methods and devices are provided for processing data using a neural network. Activations from a previous layer of the neural network are received by a layer of the neural network. Weighted values, to be applied to values of elements of the activations, are determined based on a spatial correlation of the elements and a task error output by the layer. The weighted values are applied to the values of the elements and a combined error is determined based on the task error and the spatial…
Address Translation Service Management
Granted: March 21, 2024
Application Number:
20240095184
Address translation service management techniques are described. These techniques are based on metadata that is usable to provide a hint as insight into memory access, and based on this, use of a translation lookaside buffer is optimized to control which entries are maintained in the queue and manage address translation requests.
SYSTEMS AND METHODS FOR INTERPOLATING REGISTER-BASED LOOKUP TABLES
Granted: March 21, 2024
Application Number:
20240095180
The disclosed computer-implemented method for interpolating register-based lookup tables can include identifying, within a set of registers, a lookup table that has been encoded for storage within the set of registers. The method can also include receiving a request to look up a value in the lookup table and responding to the request by interpolating, from the encoded lookup table stored in the set of registers, a representation of the requested value. Various other methods, systems, and…
TWO-LEVEL PRIMITIVE BATCH BINNING WITH HARDWARE STATE COMPRESSION
Granted: March 14, 2024
Application Number:
20240087078
Methods, devices, and systems for rendering primitives in a frame. During a visibility pass, state packets are processed to determine a register state, and the register state is stored in a memory device. During a rendering pass, the state packets are discarded and the register state is read from the memory device. In some implementations, a graphics pipeline is configured during the visibility pass based on the register state determined by processing the state packets, and the graphics…
Error Correction for Stacked Memory
Granted: March 14, 2024
Application Number:
20240087667
Error correction for stacked memory is described. In accordance with the described techniques, a system includes a plurality of error correction code engines to detect vulnerabilities in a stacked memory and coordinate at least one vulnerability detected for a portion of the stacked memory to at least one other portion of the stacked memory.
Dynamic Memory Operations
Granted: March 14, 2024
Application Number:
20240087636
Dynamic memory operations are described. In accordance with the described techniques, a system includes a stacked memory and one or more memory monitors configured to monitor conditions of the stacked memory. A system manager is configured to receive the monitored conditions of the stacked memory from the one or more memory monitors, and dynamically adjust operation of the stacked memory based on the monitored conditions. In one or more implementations, a system includes a memory and at…
FERROELECTRIC RANDOM-ACCESS MEMORY WITH ENHANCED LIFETIME, DENSITY, AND PERFORMANCE
Granted: March 14, 2024
Application Number:
20240087632
A memory device includes memory cells. A memory cell of the memory cells includes gate circuitry, a first capacitor, and a second capacitor. The gate circuitry is connected to a wordline and a bitline. The first capacitor is connected to the gate circuitry and a first drive line. The second capacitor is connected to the gate circuitry and a second drive line.
OVERLAY TREES FOR RAY TRACING
Granted: March 14, 2024
Application Number:
20240087223
A method and a processing device for performing rendering are disclosed. The method comprises generating a base hierarchy tree comprising data representing a first object and generating a second hierarchy tree representing a second object comprising shared data of the base hierarchy tree and the second hierarchy tree and difference data. The method further comprises storing the difference data in the memory without storing the shared data, and generating an overlay hierarchy tree…
LOCALITY-BASED DATA PROCESSING
Granted: March 7, 2024
Application Number:
20240078197
A data processing node includes a processor element and a data fabric circuit. The data fabric circuit is coupled to the processor element and to a local memory element and includes a crossbar switch. The data fabric circuit is operable to bypass the crossbar switch for memory access requests between the processor element and the local memory element.
SYSTEMS, METHODS, AND DEVICES FOR ADVANCED MEMORY TECHNOLOGY
Granted: March 7, 2024
Application Number:
20240078195
An electronic device includes a processor having processor circuitry and a leader memory controller, a controller coupled to the processor and having a follower memory controller, and a memory. The processor circuitry is operable to access the memory by issuing memory access requests to the leader memory controller. The leader memory controller is operable to complete the memory access requests using the follower memory controller to issue memory commands to the at least one memory die.
MEMORY CONTROLLER AND NEAR-MEMORY SUPPORT FOR SPARSE ACCESSES
Granted: March 7, 2024
Application Number:
20240078017
A data processing system includes a data processor and a memory controller receiving memory access requests from the data processor and generating at least one memory access cycle to a memory system in response to the receiving. The memory controller includes a command queue and a sparse element processor. The command queue is for receiving and storing the memory access requests including a first memory access request including a small element request. The sparse element processor is for…
VERTEX INDEX ROUTING FOR TWO LEVEL PRIMITIVE BATCH BINNING
Granted: February 29, 2024
Application Number:
20240070961
Techniques for performing rendering operations are disclosed herein. The techniques include in a coarse binning pass, generating a sorted set of draw calls, based on geometry processed through a world space pipeline and vertex indices obtained from an input assembler.
Virtually Padding Data Structures
Granted: February 29, 2024
Application Number:
20240069915
A virtual padding unit provides a virtual padded data structure (e.g., virtually padded matrix) that provides output values for a padded data structure without storing all of the padding elements in memory. When the virtual padding unit receives a virtual memory address of a location in the virtual padded data structure, the virtual padding unit checks whether the location is a non-padded location in the virtual padded data structure or a padded location in the virtual padded data…
EFFICIENT RANK SWITCHING IN MULTI-RANK MEMORY CONTROLLER
Granted: February 29, 2024
Application Number:
20240069811
A data processing system includes a memory accessing agent for generating first memory access requests, a first memory system, and a first memory controller. The first memory system includes a first three-dimensional memory stack comprising a first plurality of stacked memory dice, wherein each memory die of the first three-dimensional memory stack includes a different logical rank of a first memory channel. The first memory controller picks second memory access requests from among the…
ADAPTIVE QUANTIZATION FOR NEURAL NETWORKS
Granted: February 15, 2024
Application Number:
20240054332
Methods, devices, systems, and instructions for adaptive quantization in an artificial neural network (ANN) calculate a distribution of ANN information; select a quantization function from a set of quantization functions based on the distribution; apply the quantization function to the ANN information to generate quantized ANN information; load the quantized ANN information into the ANN; and generate an output based on the quantized ANN information. Some examples recalculate the…
Chipset Attached Random Access Memory
Granted: February 15, 2024
Application Number:
20240053891
Random access memory (RAM) is attached to an input/output (I/O) controller of a chipset (e.g., on a motherboard). This chipset attached RAM is optionally used as part of a tiered storage solution with other tiers including, for example, nonvolatile memory (e.g., a solid state drive (SSD)) or a hard disk drive. The chipset attached RAM is separate from the system memory, allowing the chipset attached RAM to be used to speed up access to frequently used data stored in the tiered storage…
METHODS FOR CONSTRUCTING PACKAGE SUBSTRATES WITH HIGH DENSITY
Granted: February 8, 2024
Application Number:
20240047228
A disclosed method can include (i) positioning a first surface of a component of a semiconductor device on a first plated through-hole, (ii) covering, with a layer of dielectric material, at least a second surface of the component that is opposite the first surface of the component, (iii) removing a portion of the layer of dielectric material covering the second surface of the component to form at least one cavity, and (iv) depositing conductive material in the cavity to form a second…
FINE-GRAINED CONDITIONAL DISPATCHING
Granted: February 8, 2024
Application Number:
20240045718
Techniques for executing workgroups are provided. The techniques include executing, for a first workgroup of a first kernel dispatch, a workgroup dependency instruction that includes an indication to prioritize execution of a second workgroup of a second kernel dispatch, and in response to the workgroup dependency instruction, dispatching the second workgroup of the second kernel dispatch prior to dispatching a third workgroup of the second kernel dispatch, wherein no workgroup…
