Virtual reality beamforming
Granted: March 23, 2021
Patent Number:
10959111
Systems, apparatuses, and methods for implementing enhanced beamforming training procedures are disclosed. A system includes a transmitter communicating over a wireless link with a receiver. To maintain a high quality of transmission over the wireless link, the transmitter and receiver perform periodic beamforming training procedures to test the various sectors of the transmit and receive antennas. In a wide sector sweep procedure, the transmitter and receiver test wide sectors to find…
Back side metallization
Granted: March 23, 2021
Patent Number:
10957669
An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The…
Hybrid render with preferred primitive batch binning and sorting
Granted: March 23, 2021
Patent Number:
10957094
A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the…
Device and method for accelerating matrix multiply operations
Granted: March 23, 2021
Patent Number:
10956536
A processing device is provided which comprises memory configured to store data and a plurality of processor cores in communication with each other via first and second hierarchical communication links. Processor cores of a first hierarchical processor core group are in communication with each other via the first hierarchical communication links and are configured to store, in the memory, a sub-portion of data of a first matrix and a sub-portion of data of a second matrix. The processor…
System and method for storing cache location information for cache entry transfer
Granted: March 23, 2021
Patent Number:
10956339
A cache stores, along with data that is being transferred from a higher level cache to a lower level cache, information indicating the higher level cache location from which the data was transferred. Upon receiving a request for data that is stored at the location in the higher level cache, a cache controller stores the higher level cache location information in a status tag of the data. The cache controller then transfers the data with the status tag indicating the higher level cache…
Retaining cache entries of a processor core during a powered-down state
Granted: March 23, 2021
Patent Number:
10956332
A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of…
Dynamic memory traffic optimization in multi-client systems
Granted: March 16, 2021
Patent Number:
10949127
Systems, apparatuses, and methods for dynamically optimizing memory traffic in multi-client systems are disclosed. A system includes a plurality of client devices, a memory subsystem, and a communication fabric coupled to the client devices and the memory subsystem. The system includes a first client which generates memory access requests targeting the memory subsystem. Prior to sending a given memory access request to the fabric, the first client analyzes metadata associated with data…
Block level rate control
Granted: March 16, 2021
Patent Number:
10951892
Systems, apparatuses, and methods for performing efficient bitrate control of video compression are disclosed. Logic in a bitrate controller of a video encoder receives a target block bitstream length for a block of pixels of a video frame. When the logic determines a count of previously compressed blocks does not exceed a count threshold, the logic selects a quantization parameter from a full range of available quantization parameters. After encoding the block, the logic determines a…
Method and apparatus for mitigating row hammer attacks
Granted: March 16, 2021
Patent Number:
10950292
An integrated circuit includes an aggressor wordline cache and logic that determines a candidate upper adjacent address and a candidate lower adjacent address of a target memory row corresponding to a read request to memory. When at least one of the candidate upper adjacent address or the candidate lower adjacent address are determined to be a victim row, the logic checks the aggressor wordline cache for a cache hit for the target memory row. When there is a cache hit in the aggressor…
Processor with accelerated lock instruction operation
Granted: March 16, 2021
Patent Number:
10949201
A processor and method for handling lock instructions identifies which of a plurality of older store instructions relative to a current lock instruction are able to be locked. The method and processor lock the identified older store instructions as an atomic group with the current lock instruction. The method and processor negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory. In some implementations, an atomic grouping…
Routing flits in a network-on-chip based on operating states of routers
Granted: March 9, 2021
Patent Number:
10944693
A system is described that includes an integrated circuit chip having a network-on-chip. The network-on-chip includes multiple routers arranged in a topology and a separate communication link coupled between each router and each of one or more neighboring routers of that router among the multiple routers in the topology. The integrated circuit chip also includes multiple nodes, each node coupled to a router of the multiple routers. When operating, a given router of the multiple routers…
Entropy agnostic data encoding and decoding
Granted: March 9, 2021
Patent Number:
10944422
Entropy agnostic data encoding includes: receiving, by an encoder, input data including a bit string; generating a plurality of candidate codewords, including encoding the input data bit string with a plurality of binary vectors, wherein the plurality of binary vectors includes a set of deterministic biased binary vectors and a set of random binary vectors; selecting, in dependence upon a predefined criteria, one of the plurality of candidate codewords; and transmitting the selected…
Offset correction for pseudo differential signaling
Granted: March 9, 2021
Patent Number:
10944368
Systems, apparatuses, and methods for performing offset correction for pseudo differential signaling are disclosed. An apparatus includes at least a sense amplifier and an offset correction circuit. The offset correction circuit generates an offset correction voltage by applying a positive or negative offset to a termination voltage. The offset correction circuit supplies the offset correction voltage to a negative input terminal of the sense amplifier. An input signal voltage is…
Semiconductor chip with reduced pitch conductive pillars
Granted: March 9, 2021
Patent Number:
10943880
Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar…
Graphics texture footprint discovery
Granted: March 9, 2021
Patent Number:
10943391
Accesses to a mipmap by a shader in a graphics pipeline are monitored. The mipmap is stored in a memory or cache associated with the shader and the mipmap represents a texture at a hierarchy of levels of detail. A footprint in the mipmap of the texture is marked based on the monitored accesses. The footprint indicates, on a per-tile, per-level-of-detail (LOD) basis, tiles of the mipmap that are expected to be accessed in subsequent shader operations. In some cases, the footprint is…
Removing or identifying overlapping fragments after z-culling
Granted: March 9, 2021
Patent Number:
10943389
Techniques for removing or identifying overlapping fragments in a fragment stream after z-culling are disclosed. The techniques include maintaining a first-in-first-out buffer that stores post-z-cull fragments. Each time a new fragment is received at the buffer, the screen position of the fragment is checked against all other fragments in the buffer. If the screen position of the fragment matches the screen position of a fragment in the buffer, then the fragment in the buffer is removed…
GPU remote communication with triggered operations
Granted: March 2, 2021
Patent Number:
10936533
Methods, devices, and systems for transmitting data over a computer communications network are disclosed. A queue of communications commands can be pre-generated using a central processing unit (CPU) and stored in a device memory of a network interface controller (NIC). Thereafter, if a graphics processing unit (GPU) has data to communicate to a remote GPU, it can store the data in a send buffer, where the location in the buffer is pointed to by a pre-generated command. The GPU can then…
Video codec data recovery techniques for lossy wireless links
Granted: March 2, 2021
Patent Number:
10938503
Systems, apparatuses, and methods for implementing data recovery techniques for lossy wireless links are disclosed. A transmitter is configured to encode a video stream and wirelessly transmit the encoded video stream to a receiver, with the video stream representing a virtual reality (VR) rendered environment. The transmitter partitions the video stream into a plurality of substream components based on frequency. Motion vector parameters are calculated for the lowest frequency substream…
Bond pads for low temperature hybrid bonding
Granted: March 2, 2021
Patent Number:
10937755
Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a…
Optimized and scalable sparse triangular linear systems on networks of accelerators
Granted: March 2, 2021
Patent Number:
10936697
A method includes storing a first portion of a sparse triangular matrix in a local memory and launching a kernel for executing a set of workgroups. The first portion includes a plurality of row blocks, and each workgroup in the set of workgroups is associated with one of the plurality of row blocks. The method also includes, for each workgroup in the set of workgroups, solving the row block. The row block is solved by, for each row segment of a first subset of row segments in the row…
