Mechanism for dynamic latency-bandwidth trade-off for efficient broadcasts/multicasts
Granted: March 2, 2021
Patent Number:
10938709
A method includes receiving, from an origin computing node, a first communication addressed to multiple destination computing nodes in a processor interconnect fabric, measuring a first set of one or more communication metrics associated with a transmission path to one or more of the multiple destination computing nodes, and for each of the destination computing nodes, based on the set of communication metrics, selecting between a multicast transmission mode and unicast transmission mode…
Security key identifier remapping
Granted: March 2, 2021
Patent Number:
10938559
Security key identifier remapping includes associating a system-level security key identifier to a local-level identifier requiring fewer bits of storage space. The remapped security key identifiers are used to receive, at a first compute complex of a processing system, a memory access request including a memory address value and a system-level security key identifier. The compute complex responds to the memory access request based on a determination of whether a security key identifier…
Die stacking for multi-tier 3D integration
Granted: February 23, 2021
Patent Number:
10930621
Various die stacks and methods of creating the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor die on a second semiconductor die of a first semiconductor wafer. The second semiconductor die is singulated from the first semiconductor wafer to yield a first die stack. The second semiconductor die of the first die stack is mounted on a third semiconductor die of a second semiconductor wafer. The third semiconductor die is…
Mechanism for supporting discard functionality in a ray tracing context
Granted: February 23, 2021
Patent Number:
10930050
Described herein is a technique for performing ray tracing. According to this technique, instead of executing intersection and/or any hit shaders during traversal of an acceleration structure to determine the closest hit for a ray, an acceleration structure is fully traversed in an invocation of a shader program, and the closest intersection with a triangle is recorded in a data structure associated with the material of the triangle. Later, a scheduler launches waves by grouping together…
Low power and low latency GPU coprocessor for persistent computing
Granted: February 23, 2021
Patent Number:
10929944
Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and…
Selective use of taint protection during speculative execution
Granted: February 23, 2021
Patent Number:
10929141
A state of a first architectural register in a processing system is changed from a first state to a second state that indicates that the first architectural register is to be monitored during speculative execution. A second architectural register in the processing system is associated with a third state in response to the first architectural register being a source register for a memory load instruction that loads data from a memory into the second architectural register during…
Distributed multi-input multi-output control theoretic method to manage heterogeneous systems
Granted: February 23, 2021
Patent Number:
10928789
A processing unit includes a plurality of subsystem control modules. Each subsystem control module includes a set of one or more inputs that receives a set of one or more external signals and a set of one or more monitored outputs from a hardware subsystem corresponding to the subsystem control module, and a set of configuration outputs for controlling one or more configuration settings of the hardware subsystem. The subsystem control module determines the one or more configuration…
Method, apparatus and system for mitigating motion sickness in a virtual reality environment
Granted: February 23, 2021
Patent Number:
10926056
Described herein are a method, system and apparatus for mitigating motion sickness in a virtual reality (VR) environment. In an implementation, the system and apparatus can include a VR controller board, a processor and a VII headset. In an implementation, the processor and VR headset are an integrated device. In general, the method includes capturing measurements using the VR controller board. The measurements are indicative of user directional movements in a physical environment…
High density cross link die with polymer routing layer
Granted: February 16, 2021
Patent Number:
10923430
Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer and an interconnect chip at least partially encased in the first molding layer. The interconnect chip has a first side and a second side opposite the first side and a polymer layer on the first side. The polymer layer includes plural conductor traces. A redistribution layer (RDL) structure is positioned on the first…
Fine granularity in clock generation
Granted: February 16, 2021
Patent Number:
10924120
An oscillator circuit includes a phase-locked loop (PLL) with a plurality of voltage controlled oscillator (VCO), a clock divider circuit receiving the VCO phase outputs and outputting a first stage clock signal with an adjustable clock period related to the PLL period based on selecting a combination of two of the VCO phase outputs. The first stage clock signal has a balanced duty cycle at frequencies that are related to the PLL frequency by even fractional divisions of the VCO phase…
Split frame rendering
Granted: February 16, 2021
Patent Number:
10922868
Improvements in the graphics processing pipeline that allow multiple pipelines to cooperate to render a single frame are disclosed. Two approaches are provided. In a first approach, world-space pipelines for the different graphics processing pipelines process all work for draw calls received from a central processing unit (CPU). In a second approach, the world-space pipelines divide up the work. Work that is divided is synchronized and redistributed at various points in the world-space…
Accelerating accesses to private regions in a region-based cache directory scheme
Granted: February 16, 2021
Patent Number:
10922237
Systems, apparatuses, and methods for accelerating accesses to private regions in a region-based cache directory scheme are disclosed. A system includes multiple processing nodes, one or more memory devices, and one or more region-based cache directories to manage cache coherence among the nodes' cache subsystems. Region-based cache directories track coherence on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. The cache directory entries…
System and method for identifying pendency of a memory access request at a cache entry
Granted: February 16, 2021
Patent Number:
10922230
A processing system indicates the pendency of a memory access request for data at the cache entry that is assigned to store the data in response to the memory access request. While executing instructions, the processor issues requests for data to the cache most proximal to the processor. In response to a cache miss, the cache controller identifies an entry of the cache to store the data in response to the memory access request, and stores an indication that the memory access request is…
Stripe based self-gating for retiming pipelines
Granted: February 9, 2021
Patent Number:
10917094
Systems, apparatuses, and methods for implementing stripe-based self-gating and change detect signal propagation for retiming pipelines are disclosed. A circuit includes one or more stripes, with each stripe including a plurality of stages of registers, with each stage only receiving input signals from the preceding stage. For a given stripe, the first stage of registers are self-gated to reduce power consumption by only clocking a group of registers when any of their input signals…
Pseudo-random logical to physical core assignment at boot for age averaging
Granted: February 9, 2021
Patent Number:
10915330
A computing device includes a processor having a plurality of cores, a core translation component, and a core assignment component. The core translation component provides a set of registers, one register for each core of the multiple processor cores. The core assignment component includes components to provide a core index to each of the registers of the core translation component according to a core assignment scheme during processor initialization. Process instructions from an…
Using loop exit prediction to accelerate or suppress loop mode of a processor
Granted: February 9, 2021
Patent Number:
10915322
A processor predicts a number of loop iterations associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component of an instruction pipeline of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer. In response to the predicted number of loop iterations being…
Providing copies of input-output memory management unit registers to guest operating systems
Granted: February 2, 2021
Patent Number:
10909053
An electronic device includes a processor that executes a guest operating system, an input-output memory management unit (IOMMU), and a main memory that stores an IOMMU backing store. The IOMMU backing store includes a separate copy of a set of IOMMU memory-mapped input-output (MMIO) registers for each guest operating system in a set of supported guest operating systems. The IOMMU receives, from the guest operating system, a communication that accesses data in a given IOMMU MMIO…
Bit error protection in cache memories
Granted: February 2, 2021
Patent Number:
10908991
A computing device having a cache memory that is configured in a write-back mode is described. A cache controller in the cache memory acquires, from a record of bit errors that are present in each of a plurality of portions of the cache memory, a number of bit errors in a portion of the cache memory. The cache controller detects a coherency state of data stored in the portion of the cache memory. Based on the coherency state and the number of bit errors, the cache controller selects an…
Device and method for accelerating matrix multiply operations as a sum of outer products
Granted: January 26, 2021
Patent Number:
10902087
A processing device is provided which includes memory and a processor comprising a plurality of processor cores in communication with each other via first and second hierarchical communication links. Each processor core in a group of the processor cores is in communication with each other via the first hierarchical communication links. Each processor core is configured to store, in the memory, one of a plurality of sub-portions of data of a first matrix, store, in the memory, one of a…
Multi-RDL structure packages and methods of fabricating the same
Granted: January 26, 2021
Patent Number:
10903168
Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.
