SELECTIVE LINER DEPOSITION FOR VIA RESISTANCE REDUCTION
Granted: December 19, 2024
Application Number:
20240420997
Methods of forming devices comprise forming a dielectric material on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include passivating a metal material at a bottom of the gap with an alkyl reactant to form a passivation layer on the metal material, the gap defined by the bottom and sidewalls comprising the dielectric material with having a barrier layer thereon. A metal liner is selectively deposited on the…
SELECTIVE SELF-ASSEMBLED MONOLAYER (SAM) REMOVAL
Granted: December 19, 2024
Application Number:
20240420996
Methods of forming microelectronic devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include forming a hardmask on the dielectric layer; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap and on the hardmask; treating the microelectronic device with a plasma to remove the self-assembled monolayer (SAM) from the hardmask; forming a…
COPPER REFLOW BY SURFACE MODIFICATION
Granted: December 19, 2024
Application Number:
20240420966
Embodiments of the disclosure relate to methods of etching a copper material. In some embodiments, the copper material is exposed to a halide reactant to form a copper halide species. The substrate is then heated to remove the copper halide species. In some embodiments, the etching methods are performed at relatively low temperatures. Additional embodiments of the disclosure relate to methods of copper gapfill. In some embodiments, a copper material within a substrate feature is exposed…
DENSIFIED SEAM-FREE SILICON-CONTAINING MATERIAL GAP FILL PROCESSES
Granted: December 19, 2024
Application Number:
20240420950
Exemplary processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. The substrate may define a feature. The methods may include forming plasma effluents of the silicon-containing precursor and depositing a silicon-containing material on the substrate. The methods may include providing a hydrogen-containing precursor to the processing region, forming plasma…
SHOWERHEAD HEATED BY CIRCULAR ARRAY
Granted: December 12, 2024
Application Number:
20240408621
Process chamber lids, processing chambers and methods using the lids are described. In some embodiments, the lid includes a showerhead with a plurality of heater segments in a peripheral region thereof. The heated showerhead minimizes temperature non-uniformity and/or minimizes heat less near the peripheral edge of a processed wafer.
AUTOMATED DIAL-IN OF ELECTROPLATING PROCESS PARAMETERS BASED ON WAFER RESULTS FROM EX-SITU METROLOGY
Granted: December 12, 2024
Application Number:
20240413011
A method of plating substrates may include receiving characteristics of a plating chamber and characteristics of a substrate to be placed in the plating chamber to be provided as inputs to a trained model. An inference operation using the trained model may be performed to generate a recipe for the plating chamber. The recipe may include characteristics of a forward plating current and characteristics of a reverse de-plating current that may be applied in order to add and remove metal to…
HIGH-PRECISION IN-SITU VERIFICATION AND CORRECTION OF WAFER POSITION AND ORIENTATION FOR ION IMPLANT
Granted: December 12, 2024
Application Number:
20240412997
Disclosed herein are approaches for in-situ verification and correction of a wafer position. In one approach, a method may include illuminating an underside of a platen positioned within a processing chamber, and detecting a perimeter edge of the platen using an imaging device positioned external to the processing chamber, above the platen. The method may further include determining, via a controller, position data for the platen based on the detected perimeter edge of the platen, and…
HIGH TEMPERATURE BIASABLE HEATER WITH ADVANCED FAR EDGE ELECTRODE, ELECTROSTATIC CHUCK, AND EMBEDDED GROUND ELECTRODE
Granted: December 12, 2024
Application Number:
20240412957
Examples of a substrate support are provided herein. In some examples, the substrate support has a ceramic electrostatic chuck having a body. The body has a first side configured to support a substrate and a second side opposite the first side. The body has a chucking electrode, an active edge electrode disposed adjacent the chucking electrode, a floating mesh disposed below the chucking electrode, a heater disposed below the floating mesh, and a ground mesh disposed below the heater,…
ION EXTRACTION OPTICS HAVING NON UNIFORM GRID ASSEMBLY
Granted: December 12, 2024
Application Number:
20240412956
A method may include receiving a beam profile function, derived from a beam density of an ion beam along a substrate plane, and generating a mirror function, based upon the beam profile function, wherein a sum of the mirror function and beam profile function generates a flat beam distribution. The method may include receiving a grid pattern for an electrode of an electrode assembly, the grid pattern comprising an array of hole locations, and calculating a normalized beam current as a…
SELECTIVE WAVEGUIDE ION IMPLANTATION TO ADJUST LOCAL REFRACTIVE INDEX FOR PHOTONICS
Granted: December 12, 2024
Application Number:
20240411085
Disclosed herein are approaches for adjusting local refractive index for photonics IC systems using selective waveguide ion implantation. In one approach, a method may include depositing an optical device film atop a base layer, patterning the optical device film into a plurality of sections, and implanting a first section of the plurality of sections of the optical device film to adjust a refractive index of the first section.
METHOD AND APPARATUS TO ENABLE DROPLET JET CLEANING AT ELEVATED TEMPERATURE
Granted: December 5, 2024
Application Number:
20240399425
Embodiments of the disclosure include an apparatus and method of cleaning a substrate. The disclosure describes a method of cleaning a substrate includes supplying a gas at a gas temperature and a gas mass flow rate to a nozzle. The method also includes supplying a liquid at a liquid temperature and a liquid mass flow rate to the nozzle. The method also includes mixing the gas with the liquid in the nozzle to form a fluid mixture having a mixture temperature of not more than about 10°…
STRUCTURE AND FABRICATION METHOD OF PERIPHERAL TRANSISTOR WITH EPI-SI CONTACTS IN MEMORY DEVICES
Granted: December 5, 2024
Application Number:
20240407170
Methods and structures to achieve low voltage (LV) and high voltage (HV) scale-down by suppressing the short channel effect of LV as well as increasing breakdown voltage of HV transistor are provided. A semiconductor device comprises a first transistor comprising a first well region of a first conductivity type, a first gate region disposed above the first well region, and a first contact region including a first epitaxial semiconductor adjacent to the first gate region; and a second…
IMPLANT SCHEME TO IMPROVE HIGH ELECTRON MOBILITY TRANSISTOR CONTACT RESISTANCE
Granted: December 5, 2024
Application Number:
20240405079
Disclosed herein are approaches for creating high electron mobility transistors with reduced contact resistance. In one approach, a method of forming a semiconductor device may include applying a first patterned mask on top of layered stack, wherein the layered stack includes a substrate, a buffer layer disposed over the substrate, a channel layer disposed above the buffer layer, and a barrier layer disposed above the channel layer. The method may further include forming, through an…
HALOGEN-FREE ETCHING OF SILICON NITRIDE
Granted: December 5, 2024
Application Number:
20240404837
Methods of semiconductor processing may include providing a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed on a substrate support within the processing region. A layer of silicon-and-nitrogen-containing material may be disposed on the substrate. The methods may include forming plasma effluents of the hydrogen-containing precursor. The methods may include contacting the layer of silicon-and-nitrogen-containing…
CHAMBERS AND COATINGS FOR REDUCING BACKSIDE DAMAGE
Granted: December 5, 2024
Application Number:
20240404835
Methods of semiconductor processing may include forming a plasma of a carbon-containing material within a processing region of a semiconductor processing chamber. The methods may include depositing a carbon-containing material on a backside of a substrate housed within the processing region of the semiconductor processing chamber. A front side of the substrate may be maintained substantially free of carbon-containing material. The methods may include performing an etch process on the…
SEAM FREE TITANIUM NITRIDE GAPFILL
Granted: December 5, 2024
Application Number:
20240404830
Embodiments of the disclosure relate to methods of depositing seam-free gapfill. In some embodiments, the gapfill consists of titanium nitride. The gapfill methods comprise forming a first layer and a second layer. The firs layer is formed without treatment or densification, while the second layer is formed with periodic treatment. The resulting gapfill in advantageously seam-free.
SCANNING ELECTRON MICROSCOPY-BASED TOMOGRAPHY OF SPECIMENS
Granted: December 5, 2024
Application Number:
20240404784
Disclosed herein is a system for non-destructive tomography of specimens. The system includes a scanning electron microscope (SEM) and a processor(s). The SEM is configured to obtain a sinogram of a tested specimen, parameterized by a vector {right arrow over (s)}, by projecting e-beams on the tested specimen, at each of a plurality of projection directions and offsets, and. for each e-beam, measuring a respective intensity of electrons returned from the tested specimen, The processor(s)…
CHIPLET AWARE ADAPTABLE QUANTIZATION
Granted: December 5, 2024
Application Number:
20240403258
A chiplet-based architecture may quantize, or reduce, the number of bits at various stages of the data path in an artificial-intelligence processor. This architecture may leverage the synergy between quantizing multiple dimensions together to greatly decrease the memory usage and data path bandwidth. Internal weights may be quantized statically after a training procedure. Accumulator bits and activation bits may be quantized dynamically during an inference operation. New hardware logic…
LIQUID PRECURSOR RECOVERY MODULE
Granted: December 5, 2024
Application Number:
20240401193
Vapor deposition precursor recovery systems and methods are provided. Methods and systems include a precursor container housing a precursor material and a carrier gas container housing a carrier gas. Systems and methods include a condenser assembly having a condenser in fluid connection with an exhaust line, a recycled precursor container, and a cooling circuit. Systems and methods include a vaporizer having one or more inlets in fluid connection with the precursor container and the…
FORMATION OF MEMORY DEVICE CHANNEL HOLES USING DOPED FILM LAYER
Granted: December 5, 2024
Application Number:
20240401189
Disclosed are approaches for to fabricating memory device channel holes using a doped film layer. One approach may include providing a substrate and forming a vertical stack over the substrate, wherein the vertical stack includes a plurality of alternating material layers. The method may further include forming a channel hole through the vertical stack, forming an oxide-nitride-oxide layer along a sidewall of the channel hole, forming a silicon layer over the oxide-nitride-oxide layer,…
