SELECTIVE DEPOSITION PROCESSES ON SEMICONDUCTOR SUBSTRATES
Granted: January 2, 2025
Application Number:
20250006485
Embodiments of the disclosure relate to methods of selectively depositing polysilicon after forming a flowable polymer film to protect a substrate surface within a feature. A first silicon (Si) layer is deposited by physical vapor deposition (PVD). The flowable polymer film is formed on the first silicon (Si) layer on the bottom. A portion of the first silicon (Si) layer is selectively removed from the top surface and the at least one sidewall. The flowable polymer film is removed. In…
MODULAR HEATING JACKET WITH REMOLDABLE INSULATOR
Granted: January 2, 2025
Application Number:
20250003076
Embodiments of the disclosure relate to heating jackets comprising a reformable insulator. The insulator may be shaped to conform to the shape of a vapor deposition precursor delivery system, or a portion thereof, and subsequently reformed to a different vapor deposition precursor delivery system, or a portion thereof. Some embodiments of the disclosure combine multiple heating modules to form a heating jacket. The heating modules contain a flexible heating element and an insulating,…
INTERFACE TUNING FOR EROSION AND CORROSION RESISTANT COATINGS FOR SEMICONDUCTOR COMPONENTS
Granted: January 2, 2025
Application Number:
20250003061
Exemplary processing methods may include providing a component for semiconductor processing to a processing region of a processing chamber. The methods may include providing one or more interface deposition precursors to the processing region. The methods may include depositing a layer of interface material on the component for semiconductor processing in the processing region. The methods may include providing one or more coating deposition precursors to the processing region. The…
FACE-UP WAFER ELECTROCHEMICAL PLANARIZATION APPARATUS
Granted: January 2, 2025
Application Number:
20250001547
Exemplary substrate electrochemical planarization apparatuses may include a chuck body defining a substrate support surface. The apparatuses may include a retaining wall extending from the chuck body. The apparatuses may include an electrolyte delivery port disposed radially inward of the retaining wall. The apparatuses may include a spindle that is positionable over the chuck body. The apparatuses may include an end effector coupled with a lower end of the spindle. The end effector may…
SUBSTRATE SAFETY SYSTEM
Granted: December 26, 2024
Application Number:
20240424685
A substrate safety system that includes (i) a control unit that is configured to trigger a substrate recovery related procedure; (ii) a sensing unit that is configured to generate, during an execution of the substrate recovery related procedure, sensed information that is indicative of one or more regions that are associated with a substrate handling station of a substrate evaluation system; (iii) an AI processing unit that is configured to apply an AI process on the sensed information…
DUAL FIELD EFFECT TRANSISTOR 4F2 CELL
Granted: December 26, 2024
Application Number:
20240431093
The present technology is generally directed to vertical dynamic random-access memory (DRAM) cells and arrays, and methods of forming such cells and arrays, that contain a shared word line between two adjacent channels. Cells include a bit line arranged in a first horizontal direction, a first channel, a second channel, and a shared word line arranged in a second horizontal direction between the first channel and the second channel. Cells include where the first channel and the second…
MEASUREMENT OF LATERAL DOPANT CONCENTRATION AND DISTRIBUTION IN HIGH ASPECT RATIO TRENCH STRUCTURES
Granted: December 26, 2024
Application Number:
20240429105
Disclosed herein are approaches for measuring lateral dopant concentration and distribution in high aspect radio trench structures. In one approach, a method may include providing a substrate including a plurality of alternating vertical structures and trenches, and removing a portion of the substrate to expose a sidewall of the first vertical structure of the plurality of structures. The method may further include directing a spectrometry beam into the sidewall of the first vertical…
INCREASED ETCH RATES OF SILICON-CONTAINING MATERIALS
Granted: December 26, 2024
Application Number:
20240429062
Exemplary methods of semiconductor processing may include providing a hydrogen-containing precursor and a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed on a substrate support within the processing region. One or more layers of silicon-containing material may be disposed on the substrate. The methods may include forming plasma effluents of the hydrogen-containing precursor and the fluorine-containing precursor. The…
REDUCED STRAIN AND STOP LAYER FOR Si/SiGe EPI STACKS
Granted: December 26, 2024
Application Number:
20240429048
A semiconductor device and a method for manufacturing thereof. A substrate is provided. At least one silicon layer is formed on top of the substrate. At least one silicon-germanium layer is formed on top of at least one silicon layer. At least one silicon-germanium layer includes at least one n-type dopant. The semiconductor device having at least one silicon layer and at least one silicon-germanium layer is formed.
HALOGEN-FREE MOLYBDENUM-CONTAINING PRECURSORS FOR DEPOSITION OF MOLYBDENUM
Granted: December 26, 2024
Application Number:
20240425536
Exemplary methods of semiconductor processing, such as methods of depositing a molybdenum-containing material on a substrate, may include providing a molybdenum-containing precursor to a processing region of a semiconductor processing chamber in which the substrate is located. The molybdenum-containing precursor may include a molybdenum complex according to Compound I: R may be methyl or ethyl, R? may be methyl or ethyl, R? may be methyl, ethyl, or propyl, and n may be equal to 1 or…
DISCHARGING A REGION OF A SAMPLE
Granted: December 19, 2024
Application Number:
20240420917
A system for discharging a region of a sample, the system includes (i) illumination optics that is configured to discharge the region by illuminating the region of the sample with a laser pulse during an illumination iteration; and (ii) a timing circuit that is configured to trigger the illumination iteration to occur at a timing that is based on one or more timing constraints associated with a scanning of the region by an electron beam.
SELECTIVE LINER DEPOSITION FOR VIA RESISTANCE REDUCTION
Granted: December 19, 2024
Application Number:
20240420997
Methods of forming devices comprise forming a dielectric material on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include passivating a metal material at a bottom of the gap with an alkyl reactant to form a passivation layer on the metal material, the gap defined by the bottom and sidewalls comprising the dielectric material with having a barrier layer thereon. A metal liner is selectively deposited on the…
SELECTIVE SELF-ASSEMBLED MONOLAYER (SAM) REMOVAL
Granted: December 19, 2024
Application Number:
20240420996
Methods of forming microelectronic devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include forming a hardmask on the dielectric layer; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap and on the hardmask; treating the microelectronic device with a plasma to remove the self-assembled monolayer (SAM) from the hardmask; forming a…
NESTED-LOOP PLASMA ENHANCED ATOMIC LAYER DEPOSITION
Granted: December 19, 2024
Application Number:
20240420952
Exemplary methods of semiconductor processing may include iteratively repeating a deposition cycle several times on a substrate disposed within a processing region of a semiconductor processing chamber. Each deposition cycle may include depositing a silicon-containing material on the substrate and exposing the silicon-containing material to a first oxygen plasma to convert the silicon-containing material to a silicon-and-oxygen-containing material. After the iterative repeating of the…
DOPED SILICON OXIDE FOR BOTTOM-UP DEPOSITION
Granted: December 19, 2024
Application Number:
20240420949
Exemplary processing methods may include i) providing one or more deposition precursors to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may include one or more features defining one or more sidewalls. The methods may include ii) forming plasma effluents of the one or more deposition precursors. The methods may include iii) contacting the substrate with the plasma effluents of the one or more deposition…
SELECTIVE CARBON DEPOSITION ON TOP AND BOTTOM SURFACES OF SEMICONDUCTOR SUBSTRATES
Granted: December 19, 2024
Application Number:
20240420948
Semiconductor processing methods are described that include providing a substrate to a reaction chamber, where the substrate includes substrate trenches that have a top surface and a bottom surface. A deposition gas that includes a carbon-containing gas and a nitrogen-containing gas flows into a plasma excitation region of the reaction chamber. A deposition plasma having an electron temperature less than or about 4 eV is generated from the deposition gas. The methods further include…
IN-SITU ETCH AND INHIBITION IN PLASMA ENHANCED ATOMIC LAYER DEPOSITION
Granted: December 19, 2024
Application Number:
20240420934
Exemplary methods of semiconductor processing may include methods for nonconformally building up silicon-and-oxygen-containing material where the top of the feature preferentially fills at a slower rate as compared to the bottom of the feature. Such methods may include iterative nonconformal etching operations and/or iterative nonconformal inhibition operations. For example, after building up a layer comprising silicon-and-oxygen-containing material, the layer may be nonconformally…
RESISTIVITY-CONTROLLED DIELECTRIC MATERIALS FOR SUBSTRATE SUPPORTS WITH IMPROVED HIGH TEMPERATURE CHUCKING
Granted: December 19, 2024
Application Number:
20240420933
Substrate support assembly and methods of making such substrate support assemblies are provided. Substrate support assemblies include an electrostatic chuck body defining a substrate support surface, a support stem coupled with the electrostatic chuck body, and an electrode embedded within the electrostatic chuck body. Substrate support surfaces exhibit a resistivity of 1×108 ?-cm to 1×1011 ?-cm at a temperature of greater than 650° C. Substrate support surfaces can include a…
SEMICONDUCTOR MANUFACTURING PROCESS CHAMBER COOLING FLANGE FOR REMOTE PLASMA SOURCE SUPPLY
Granted: December 19, 2024
Application Number:
20240420924
Cooling flanges and semiconductor manufacturing processing chamber comprising the cooling flanges are disclosed. The cooling flanges comprise a flange body with a gas channel extending through the length thereof. The gas channel has an inlet funnel, a middle channel and an outlet funnel with a purge gas inlet in a side of the flange body. The purge gas inlet connects to the middle channel of the gas channel.
METHOD OF ASSEMBLING DRIFT TUBE ASSEMBLIES IN ION IMPLANTORS
Granted: December 19, 2024
Application Number:
20240420919
An ion implantation system including an ion source for generating an ion beam, an end station for holding a substrate to be implanted by the ion beam, and a linear accelerator disposed between the ion source and the end station and adapted to accelerate the ion beam, the linear accelerator comprising at least one acceleration stage including a resonator coil coupled to a drift tube assembly, the drift tube assembly including a first drift tube coupled to a first end of a first insulting…
