3D DRAM Access Transistor
Granted: November 7, 2024
Application Number:
20240373622
Disclosed herein are approaches for forming a 3-D dynamic random-access memory device having reduced floating body effect. In one example, a method may include forming a plurality of layers stacked in a first direction, the plurality of layers including a gate layer formed over a first oxide layer, and a source/drain (S/D) layer between a set of gate oxide layers. The set of gate oxide layers may be formed over the gate layer, and the S/D layer may include a source and a drain on…
ELECTROSTATIC CLAMP HAVING CHARGE CONTROL ASSEMBLY
Granted: November 7, 2024
Application Number:
20240371675
An electrostatic clamp system may include a conductive base; a ceramic body, having an inner side that is attached to the conductive base, and an outer side to face a substrate, the ceramic body including an electrode assembly; and a charge control assembly, the charge control assembly defining an electrically conductive structure that is isolated from the electrode assembly and extends through the conductive base to an upper surface of the outer side of the ceramic body.
LIFT ASSEMBLY FOR SEMICONDUCTOR MANUFACTURING PROCESSING CHAMBER
Granted: November 7, 2024
Application Number:
20240371673
Apparatuses and methods for loading and unloading substrates from a semiconductor manufacturing processing chamber are described. Some embodiments advantageously provide improved lift assemblies (e.g., lift ring designs) for centering lift pins in semiconductor processing chambers by allowing for unconstrained translation of the lift pins in the x-y plane. Some embodiments advantageously prevent lift pin tilting. Some embodiments advantageously provide a seal between the top end portion…
HIGH-THROUGHPUT PLASMA LID FOR SEMICONDUCTOR MANUFACTURING PROCESSING CHAMBERS
Granted: November 7, 2024
Application Number:
20240371613
Semiconductor manufacturing processing chambers having an RF isolator between the support ring and the showerhead and/or an RF gasket between the showerhead and the gas funnel are described. A cap insert with a cap housing around the cap insert is on the gas funnel and an RF feed is in contact with the showerhead. A substrate support can be included and may have an RF return path directed through the substrate support.
PROCESSING CHAMBER WITH GAS RECYCLING
Granted: November 7, 2024
Application Number:
20240368764
Semiconductor manufacturing processing chambers with recycling capability and methods of recycling a chemical precursor are described. The processing chamber comprises a chamber body with a substrate support. The substrate support is spaced form the chamber lid to create a process region. A gas inlet provides a flow of gas to the process region and a recirculation plenum is in fluid communication with the process region. At least one fast-acting valve is connected to the recirculation…
METHODS FOR BOW COMPENSATION USING TENSILE NITRIDE
Granted: October 31, 2024
Application Number:
20240363357
Embodiments of the present technology may include semiconductor processing methods. The methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-containing precursor and a nitrogen-containing precursor. A substrate including one or more materials may be disposed within the processing region. The substrate may be characterized by a first bowing of the substrate. The methods may include…
3D NAND CELLS WITH ENHANCED ERASE SPEED THROUGH DIPOLE ENGINEERING AND METHODS OF MAKING THE SAME
Granted: October 31, 2024
Application Number:
20240365551
Exemplary semiconductor structures may include a substrate. The structures may include a first layer of silicon-and-oxygen-containing material overlying the substrate. The structures may include a second layer of silicon-and-oxygen-containing material. The structures may include a first layer of metal-and-oxygen-containing material between the first layer of silicon-and-oxygen-containing material and the second layer of silicon-and-oxygen-containing material. The first layer of…
WORDLINE CONTACT FORMATION FOR NAND DEVICE
Granted: October 31, 2024
Application Number:
20240365545
Disclosed are approaches for wordline contact formation for 3D NAND devices. Methods may include providing a film stack of alternating first layers and second layers, forming a first lithography mask over the film stack, and performing a first series of alternating lithography and etch processes to form an array of contact opening pairs in the film stack, wherein an opening through the first lithography mask is expanded in a first direction following each etch process, and wherein a…
MULTI-THRESHOLD VOLTAGE INTEGRATION SCHEME FOR SEMICONDUCTOR DEVICES
Granted: October 31, 2024
Application Number:
20240363723
Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. The method comprises forming a P-dipole stack and an N-dipole stack on a semiconductor substrate by: depositing an interfacial layer (e.g., silicon oxide (SiOx)) on…
LOW-ENERGY UNDERLAYER FOR ROOM TEMPERATURE PHYSICAL VAPOR DEPOSITION OF ELECTRICALLY CONDUCTIVE FEATURES
Granted: October 31, 2024
Application Number:
20240363407
Embodiments of the present disclosure generally relate to a method for forming an electrically conductive feature on a substrate. In one embodiment, the method includes forming a first conductive layer via physical vapor deposition (PVD) in an opening of a substrate. The first conductive layer has a thickness of less than 20 angstroms. The method further includes forming a second conductive layer via PVD on the first conductive layer. The first conductive layer and the second conductive…
SILICON CHANNEL FOR BONDED 3D NAND DEVICES
Granted: October 31, 2024
Application Number:
20240363345
A method for manufacturing a memory device includes depositing a seed layer in a memory hole extending through a memory stack. The seed layer includes particles, such as silicon particles. The seed layer is etched to produce etched particles. The etched particles act as nuclei for the growth of a crystalline channel material in the memory hole.
METHODS FOR FORMING LOW-K DIELECTRIC MATERIALS
Granted: October 31, 2024
Application Number:
20240363337
Semiconductor processing methods are described for forming low-? dielectric materials. The methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-carbon-and-hydrogen-containing precursor. A substrate may be disposed within the processing region. The methods may include forming plasma effluents of the deposition precursors. The methods may include depositing a layer of…
AMORPHOUS CARBON FOR GAP FILL
Granted: October 31, 2024
Application Number:
20240363332
Methods for depositing an amorphous carbon layer on a substrate and for filling a substrate feature with an amorphous carbon gap fill are described. The method comprises performing a deposition cycle comprising: introducing a hydrocarbon source into a processing chamber; introducing a plasma initiating gas into the processing chamber; generating a plasma in the processing chamber at a temperature of greater than 600° C.; forming an amorphous carbon layer on a substrate with a deposition…
METHOD OF PLASMA CLEANING OF FUSED SILICA TUBES
Granted: October 31, 2024
Application Number:
20240363317
Methods and apparatus for cleaning a dielectric tube are described. The dielectric tube is exposed to a cleaning gas comprising a fluorine-containing compound and a microwave plasma is generated. The dielectric tube is cleaned to restore transparency and increase electronic coupling between the microwave waveguide and the plasma through the dielectric tube.
WORDLINE CONTACT FORMATION FOR NAND DEVICE
Granted: October 31, 2024
Application Number:
20240363150
Disclosed are approaches for wordline contact formation for 3D NAND devices. Methods may include providing a film stack of alternating first layers and second layers, forming a first lithography mask over the film stack, and performing a first series of alternating lithography and etch processes to form an array of contact opening pairs in the film stack, wherein an opening through the first lithography mask is expanded in a first direction following each etch process, and wherein a…
CONTROL OF LIQUID DELIVERY IN AUTO-REFILL SYSTEMS
Granted: October 31, 2024
Application Number:
20240360561
An system, method and software for controlling processes of an auto-refill system of an ampoule including one or more sensors configured to determine one or more liquid level heights within the ampoule. The auto-refill system having a state machine configured to control the auto-refill system, the state machine having one or more states for refilling the ampoule.
HALIDE AND ORGANIC PRECURSORS FOR METAL DEPOSITION
Granted: October 31, 2024
Application Number:
20240360557
Methods for depositing metal films using a metal halide and metal organic precursors are described. The substrate is exposed to a first metal precursor and a second metal precursor to form the metal film. The exposures can be sequential or simultaneous. The metal films are relatively pure with a low carbon content.
DEPOSITION APPARATUS AND METHODS USING STAGGERED PUMPING LOCATIONS
Granted: October 31, 2024
Application Number:
20240360553
Processing chambers and methods of use comprising a plurality of processing regions bounded around an outer peripheral edge by one or more vacuum channel. A first processing region has a first vacuum channel with a first outer diameter and a second processing region has a second vacuum channel with a second outer diameter, the first outer diameter being less than the second outer diameter.
PLASMA BASED FILM MODIFICATION FOR SEMICONDUCTOR DEVICES
Granted: October 24, 2024
Application Number:
20240352575
Disclosed herein are approaches for treating a film layer of a semiconductor device to modify an etch resistance of the film later. In one approach, a method may include forming a first film over a substrate base, depositing a second film over the first film, and introducing an inert species into the second film while the second film is deposited over the first film, wherein the inert species increases an etch-resistance of a first portion of the first film. The method may further…
SIDE PUMPING CHAMBER AND DOWNSTREAM RESIDUE MANAGEMENT HARDWARE
Granted: October 24, 2024
Application Number:
20240352580
Exemplary semiconductor processing chambers may include a chamber body having sidewalls and a base. The chambers may include a pumping liner seated atop the chamber body. The pumping liner may at least partially define an annular pumping plenum and at least one exhaust aperture that fluidly couples the pumping plenum with an interior of the chamber body. The chambers may include a purge ring seated below the pumping liner. The purge ring may define an annular channel that extends about a…
