INTEGRATED DIPOLE REGION FOR TRANSISTOR
Granted: October 3, 2024
Application Number:
20240332008
Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of…
MEMORY DEVICES AND METHODS OF FORMING THE SAME
Granted: October 3, 2024
Application Number:
20240334683
Memory devices and methods of manufacturing memory devices are described herein. The memory devices include a bitline metal stack on a surface comprising a matrix of conductive bitline contacts (e.g., polysilicon) and insulating dielectric islands (e.g., silicon nitride (SiN)). The bitline metal stack comprises one or more of titanium (Ti), tungsten (W), tungsten nitride (WN), tungsten silicide (WS), or tungsten silicon nitride (WSiN). The memory devices include a bitline metal layer…
METHODS OF REDUCING BACKSIDE CONTACT RESISTANCE
Granted: October 3, 2024
Application Number:
20240332388
One or more embodiments of the disclosure are directed to methods of forming semiconductor devices, e.g., gate-all-around (GAA) transistors that are used in FEOL and/or BEOL processes. The processes described herein may be integrated and performed in any suitable cluster tool. Some embodiments of the disclosure are directed to cavity shaping processes. Further embodiments of the disclosure are directed to logic transistors with wrap-around backside source/drain contact.
GRADIENT METAL LINER FOR INTERCONNECT STRUCTURES
Granted: October 3, 2024
Application Number:
20240332075
Methods of forming microelectronic devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a first self-assembled monolayer (SAM) on the bottom of the gap; forming a barrier layer on the dielectric layer; selectively depositing a second self-assembled monolayer (SAM) on the barrier layer and on the bottom of the gap; treating the…
PROTECTIVE CAPPING LAYER FOR AREA SELECTIVE DEPOSITION
Granted: October 3, 2024
Application Number:
20240332072
Described are methods of forming a protective capping layer on a metal layer of a semiconductor substrate. A metal layer is deposited using a metal precursor and a reactant pulsed to form the metal layer having a reactive surface. The number of cycles can be in a range of from 1 to 10 cycles or from 2 to 5 cycles or from 2 to 100 cycles. The metal layer is then exposed to a long chain precursor (e.g., primary amines, alcohols, thiols, phosphines, selenols) and a metal precursor to form a…
METHOD FOR ETCHING HIGH ASPECT RATIO STRUCTURES
Granted: October 3, 2024
Application Number:
20240332031
A method and system for etching high aspect ratio structures in a semiconducting processing chamber are disclosed herein. In one example, a method of patterning a substrate comprises etching the substrate to form a recess, depositing a passivation layer on sidewalls of the recess, treating the passivation layer, and etching the recess to a second depth. The substrate etch forms a recess to a first depth, the substrate having a mask layer disposed thereon. The treating of the passivation…
COMPRESSIVE FILMS FOR LARGE AREA GAPFILL
Granted: October 3, 2024
Application Number:
20240332028
Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the semiconductor processing chamber. The methods may include forming a silicon-containing material on the substrate. The silicon-containing material may be characterized by a stress of greater than or about ?200 MPa. The methods may include annealing the substrate at a temperature of greater…
SILICON-AND-GERMANIUM ETCHING
Granted: October 3, 2024
Application Number:
20240332027
Exemplary methods of semiconductor processing may include providing a first fluorine-containing precursor to a remote plasma system of a semiconductor processing chamber. The methods may include generating plasma effluents of the first fluorine-containing precursor in the remote plasma system. The methods may include providing plasma effluents of the first fluorine-containing precursor to a processing region of the semiconductor processing chamber. The methods may include providing a…
DOPING BY MOLECULAR LAYER DEPOSITION
Granted: October 3, 2024
Application Number:
20240332014
Molecular layer deposition (MLD) is used to provide conformal and uniform doping technology for HAR and reentrant structures. MLD is used to deposit a conformal carbon-based film that contains a doping element. Thermal annealing is then used to make the doping element diffuse into the semiconductor material. For HAR structures, a conformal layer is used with low temperature doping, precise control, and the carbon-based film can be easily removed during doping or after doping. The amount…
ION IMPLANTATION FOR REDUCED ROUGHNESS OF SILICON NITRIDE
Granted: October 3, 2024
Application Number:
20240332009
Exemplary methods of semiconductor processing may include forming a layer of silicon nitride on a semiconductor substrate. The layer of silicon nitride may be characterized by a first roughness. The methods may include performing a post-deposition treatment on the layer of silicon nitride. The methods may include reducing a roughness of the layer of silicon nitride such that the layer of silicon nitride may be characterized by a second roughness less than the first roughness.
METHODS TO IMPROVE QUALITY SILICON-CONTAINING MATERIALS
Granted: October 3, 2024
Application Number:
20240332006
Exemplary methods of forming a silicon-and-carbon-containing material may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor to the processing region. The methods may include generating plasma effluents of the silicon-containing precursor and plasma effluents of the…
METHODS FOR DEPOSITING DIELECTRIC FILMS WITH INCREASED STABILITY
Granted: October 3, 2024
Application Number:
20240332005
Embodiments include semiconductor processing methods to form dielectric films on semiconductor substrates are described. The methods may include providing a silicon-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The methods may include providing an inert precursor to the processing region of the semiconductor processing chamber. The methods may include…
RF PULSING ASSISTED TUNGSTEN-CONTAINING FILM DEPOSITION
Granted: October 3, 2024
Application Number:
20240332003
Exemplary semiconductor processing methods may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber, the deposition precursors may be or include a tungsten-containing precursor. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma of the one or more deposition precursors in the processing region. The plasma may be at least partially formed by…
ATOMIC LAYER DEPOSITION OF SILICON-CARBON-AND-NITROGEN-CONTAINING MATERIALS
Granted: October 3, 2024
Application Number:
20240332001
Exemplary methods of semiconductor processing may include providing a first precursor to a semiconductor processing chamber. A substrate may be disposed within a processing region of the semiconductor processing chamber. The substrate may define a feature. The methods may include contacting the substrate with the first precursor. The contacting may form a first portion of a silicon-carbon-and-nitrogen-containing material on the substrate. The methods may include providing a second…
DOPED SILICON-CONTAINING MATERIALS WITH INCREASED ELECTRICAL, MECHANICAL, AND ETCH CHARACTERISTICS
Granted: October 3, 2024
Application Number:
20240332000
Exemplary methods of semiconductor processing may include providing deposition precursors to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The deposition precursors may include a silicon-containing precursor. The methods may include providing a dopant precursor to the processing region of the semiconductor processing chamber. The dopant precursor may include a phosphorous-containing precursor. The methods may include…
DENSIFIED SEAM-FREE SILICON GAP FILL PROCESSES
Granted: October 3, 2024
Application Number:
20240331975
Exemplary processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. The substrate may define a feature within the substrate. The methods may include forming plasma effluents of the silicon-containing precursor. The methods may include depositing a silicon-containing material on the substrate. The methods may include providing a hydrogen-containing precursor to…
THERMAL PROCESSING CHAMBER STATE BASED ON THERMAL SENSOR READINGS
Granted: October 3, 2024
Application Number:
20240327988
A method of characterizing thermal processing chambers may include training a model using temperature rate-of-change data from existing thermal processing chambers. A supervised learning process may label the rate-of-change data based on deposition profiles on substrates. The trained model may be used to characterize another chamber to determine if the predicted performance will match the chambers used to train the model. An inert process using carrier gasses may be used to capture…
SELECTIVE OXIDATION PROCESSES FOR GATE-ALL-AROUND TRANSISTORS
Granted: September 26, 2024
Application Number:
20240321584
Semiconductor devices, such as gate-all-around (GAA) devices, and methods of forming semiconductor devices are described. Selective oxidation processes that are useful in front-end of line (FEOL) and back-end of line (BEOL) applications and processes are also described. In FEOL processes, for example, selective oxidation protects silicon germanium (SiGe) layers during etching silicon (Si) channel recess when there is no dielectric inner spacer present. In BEOL processes, for example,…
PRECLEAN AND ENCAPSULATION OF MICROLED FEATURES
Granted: September 26, 2024
Application Number:
20240322073
Method for cleaning and encapsulating microLED features are disclosed. Some embodiments provide for a wet clean process and a dry clean process to remove contaminants from the microLED feature. Some embodiments provide for the encapsulation of a clean microLED feature. Some embodiments provide improved crystallinity of the microLED feature and the capping layer. Some embodiments provide improved EQE of microLED devices formed from the disclosed microLED features.
ULTRA-THIN LAYERS BY SELECTIVE PASSIVATION
Granted: September 26, 2024
Application Number:
20240321633
Methods for depositing ultra-thin films are disclosed. Some embodiments of the disclosure utilize ultra-thin films as barrier layers, liner layers, or nucleation layers to decrease interconnect resistance. Some embodiments advantageously provide continuous films with thicknesses of less than or equal to about 20 ?. Some embodiments advantageously provide films with decreased roughness.
