DEPOSITION OR ETCH CHAMBER WITH COMPLETE SYMMETRY AND HIGH TEMPERATURE SURFACES
Granted: August 29, 2024
Application Number:
20240290638
Exemplary semiconductor processing systems may include a chamber having a body having a sidewall and a base. The chamber may include a pumping liner atop the body and a faceplate atop the pumping liner. The chamber may include a substrate support. The substrate support may include a plate and a shaft. The chamber may include a seal plate coupled with the shaft below the plate. The seal plate may have a greater diameter than the plate. The seal plate may include an RF gasket outward of…
PROCESSING METHODS TO IMPROVE ETCHED SILICON-AND-GERMANIUM-CONTAINING MATERIAL SURFACE ROUGHNESS
Granted: August 29, 2024
Application Number:
20240290623
Exemplary semiconductor processing methods may include providing a pre-treatment precursor to a processing a remote plasma system of a semiconductor processing chamber. The methods may include generating plasma effluents of the pre-treatment precursor in the remote plasma system. The methods may include flowing plasma effluents of the pre-treatment precursor to a processing region of the semiconductor processing chamber. A substrate including alternating layers of material may be…
SYSTEMS AND METHODS FOR DEPOSITING LOW-K DIELECTRIC FILMS
Granted: August 29, 2024
Application Number:
20240290611
Exemplary methods of forming a silicon-and-carbon-containing material may include flowing a silicon-oxygen-and-carbon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma within the processing region of the silicon-and-carbon-containing precursor. The plasma may be formed at a frequency less than 15 MHz (e.g., 13.56 MHz).…
MOVEABLE SUPPORT TO SECURE ELECTRICALLY CONDUCTIVE AND NONCONDUCTIVE SAMPLES IN A VACUUM CHAMBER
Granted: August 29, 2024
Application Number:
20240290572
A chuck that supports a sample in a processing chamber and comprises: a support plate formed from a dielectric material, the support plate including an upper planar support surface sized and shaped to retain a substrate disposed on the support plate; one or more electrodes disposed within the support plate proximate the upper planar support surface; a plurality of lift pin holes formed completely through the support plate; a plurality of stub cavities formed within the support plate,…
METHODS OF REDUCING OR ELIMINATING DEPOSITS IN AN ELECTROPLATING SYSTEM
Granted: August 29, 2024
Application Number:
20240287702
The present technology includes methods for reducing the formation of insoluble deposits in a plating system or a surface thereof. The methods include reducing a volume of a plating solution having a first pH in a plating bath from a first volume to a second volume, adding a replenishment agent to the plating solution to increase the volume of the plating solution from the second volume to the first volume. The replenishment agent is characterized by a second pH, where the second pH…
METHODS FOR FORMING IMPURITY FREE METAL ALLOY FILMS
Granted: August 29, 2024
Application Number:
20240287678
Methods of depositing a metal film by exposing a substrate surface to a halide precursor and an organosilane reactant are described. The halide precursor comprises a compound of general formula (I): MQzRm, wherein M is a metal, Q is a halogen selected from Cl, Br, F or I, z is from 1 to 6, R is selected from alkyl, CO, and cyclopentadienyl, and m is from 0 to 6. The aluminum reactant comprises a compound of general formula (II) or general formula (III): wherein R1, R2, R3, R4, R5,…
LOUVER DESIGN FOR ELIMINATING LINE OF SIGHT
Granted: August 22, 2024
Application Number:
20240282605
An apparatus and system for minimizing particle return to the processing area of a processing chamber are disclosed herein. In one example, a particle shield for a semiconductor vacuum processing chamber includes an annular ring, a plurality of rib supports, and a plurality of louver fins. The annular ring has top surface, a bottom surface, and a plurality of cutaways. The top surface has an upper outer portion and a lower inner portion. The plurality of rib supports are disposed on and…
POLARIZER-FREE LED DISPLAYS
Granted: August 22, 2024
Application Number:
20240284703
Exemplary subpixel structures include a directional light-emitting diode structure characterized by a full-width-half-maximum (FWHM) of emitted light having a divergence angle of less than or about 10°. The subpixel structure further includes a lens positioned a first distance from the light-emitting diode structure, where the lens is shaped to focus the emitted light from the light-emitting diode structure. The subpixel structure still further includes a patterned light absorption…
SILICON SUPER JUNCTION STRUCTURES FOR INCREASED THROUGHPUT
Granted: August 22, 2024
Application Number:
20240282813
A super junction device with an increased manufacturing throughput may be formed by forming narrow trenches lined with a P-type liner and rapidly filled with a passive fill material. Instead of etching trenches with aspect ratio large enough to reliably fill with doped P-type material, the aspect ratio of the trench may be reduced to shrink the size of the device. This smaller trench may then be lined with a relatively thin (e.g., about 1 ?m to about 2 ?m) P-type liner instead of…
SILICON SUPER JUNCTION STRUCTURES FOR INCREASED VOLTAGE
Granted: August 22, 2024
Application Number:
20240282809
A super junction device with an increased voltage rating may be formed by decreasing the width of the P-type region and increasing the doping concentration, while also increasing the height of the overall device. However, instead of etching a trench in the N-type material to fill with the P-type material, a trench may be etched for both the P-type region and an adjacent N-type region. This allows the height of the overall device to be increased while maintaining a feasible aspect ratio…
TREATMENTS TO IMPROVE ETCHED SILICON-AND-GERMANIUM-CONTAINING MATERIAL SURFACE ROUGHNESS
Granted: August 22, 2024
Application Number:
20240282585
Exemplary semiconductor processing methods may include providing a treatment precursor to a processing a remote plasma system of a semiconductor processing chamber. The methods may include generating plasma effluents of the treatment precursor in the remote plasma system. The methods may include flowing plasma effluents of the treatment precursor to a processing region of the semiconductor processing chamber. A substrate including alternating layers of material may be disposed within the…
PHYSICAL LAYOUT SYNTHESIS FOR STANDARD CELLS USING SLICE LAYOUTS
Granted: August 22, 2024
Application Number:
20240281584
A method of automatically generating standard cells may include receiving a definition of a circuit for a standard cell. The definition may include one or more semiconductor devices. The method may also include identifying a plurality of slices that implement a device in the one or more semiconductor devices. Each of the plurality of slices may include a partial layout for the device. The method may further include combining more than one of the plurality of slices into a combined layout…
MOLYBDENUM(0) PRECURSORS FOR DEPOSITION OF MOLYBDENUM FILMS
Granted: August 22, 2024
Application Number:
20240279804
Molybdenum(0) precursors and methods of forming molybdenum-containing films on a substrate surface are described. The molybdenum(0) precursors have a purity of greater than or equal to 90% molybdenum (Mo) on a molar basis. The substrate is exposed to a molybdenum(0) precursor and a reactant to form a molybdenum-containing film having greater than or equal to 80% molybdenum (Mo) on an atomic basis. In some embodiments, the molybdenum-containing film has greater than or equal to 80%…
UNIFORM SIGE CHANNEL IN NANOSHEET ARCHITECTURE
Granted: August 15, 2024
Application Number:
20240274724
Horizontal gate-all-around devices and methods of manufacture are described. The hGAA devices comprise a semiconductor material between source regions and drain regions of the device. The method includes formation of a cladding material on a first material followed by forming a tensile film on the cladding layer. The strained tensile film results in a uniform SiGe channel.
PADDLE CHAMBER WITH ANTI-SPLASHING BAFFLES
Granted: August 15, 2024
Application Number:
20240271312
Electroplating systems according to embodiments of the present technology may include a plating chamber configured to deposit metal material onto substrates positioned in the plating chamber. The plating chamber may include a rotor and a vessel. The electroplating systems may include at least one of baffle positioned in the plating chamber. The at least one baffle may define a plurality of slots. The at least one baffle may be configured to limit or prevent fluid from splashing the rotor…
SEMICONDUCTOR DEVICE PATTERNING METHODS
Granted: August 15, 2024
Application Number:
20240271272
Methods of patterning semiconductor devices comprising selective deposition methods are described. A blocking layer is deposited on a metal surface of a semiconductor device before deposition of a dielectric material on a dielectric surface. Methods include exposing a substrate surface including a metal surface and a dielectric surface to a heterocyclic reactant comprising a headgroup and a tailgroup in a processing chamber and selectively depositing the heterocyclic reactant on the…
INDEX POLISHING FOR PROCESS CONTROL SIGNAL AND WAFER UNIFORMITY
Granted: August 15, 2024
Application Number:
20240269796
A method of performing polishing processes on substrates may include receiving a substrate in a known alignment in a carrier head of a polishing station for a polishing process. The polishing process may cause the substrate in the carrier head to be polished by a polishing pad on a platen such that the substrate passes over one or more sensors in the platen along one or more predetermined sensor paths relative to the known alignment of the substrate. The method may also include causing…
SELECTIVE ETCHING OF SILICON-CONTAINING MATERIAL RELATIVE TO METAL-DOPED BORON FILMS
Granted: August 8, 2024
Application Number:
20240266185
Exemplary semiconductor processing methods may include depositing a metal-doped boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The metal-doped boron-containing material may include a metal dopant comprising tungsten. The substrate may include a silicon-containing material. The methods may include depositing one or more additional materials over the metal-doped boron-containing material. The one or more additional…
V-NAND STACKS WITH DIPOLE REGIONS
Granted: August 8, 2024
Application Number:
20240268108
A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.
SECURING A WAFER TO A CHUCK
Granted: August 8, 2024
Application Number:
20240266204
A system that includes a vacuum module that includes a first vacuum source, a first vacuum propagation path, a second vacuum source, and a second vacuum propagation path. The first vacuum source is configured to provide first vacuum of a first vacuum level, via the first vacuum propagation path, to a chuck. The chuck is mounted on a mechanical stage. The second vacuum source is configured to provide second vacuum at a second vacuum level, via the second vacuum propagation path, to the…
