RESONATOR, LINEAR ACCELERATOR CONFIGURATION AND ION IMPLANTATION SYSTEM HAVING ROTATING EXCITER
Granted: January 25, 2024
Application Number:
20240032183
An exciter for a high frequency resonator. The exciter may include an exciter coil inner portion, extending along an exciter axis, an exciter coil loop, disposed at a distal end of the exciter coil inner portion. The exciter may also include a drive mechanism, including at least a rotation component to rotate the exciter coil loop around the exciter axis.
APPARATUS, SYSTEM AND METHOD FOR ENERGY SPREAD ION BEAM
Granted: January 25, 2024
Application Number:
20240029997
An ion implanter may include an ion source, arranged to generate a continuous ion beam, a DC acceleration system, to accelerate the continuous ion beam, as well as an AC linear accelerator to receive the continuous ion beam and to output a bunched ion beam. The ion implanter may also include an energy spreading electrode assembly, to receive the bunched ion beam and to apply an RF voltage between a plurality of electrodes of the energy spreading electrode assembly, along a local…
METHOD TO REDUCE LINE EDGE ROUGHNESS FOR EUV PHOTORESIST PATTERN
Granted: January 25, 2024
Application Number:
20240027912
Methods of depositing a conformal carbon-containing film on an EUV photoresist to reduce line edge roughness (LER) are described. Exemplary processing methods may include flowing a first precursor over a patterned EUV surface to form a first portion of an initial carbon-containing film on the structure. The methods may include removing a first precursor effluent from the patterned EUV photoresist. A second precursor may then be flowed over the patterned EUV photoresist to react with the…
CONFORMAL MOLYBDENUM DEPOSITION
Granted: January 25, 2024
Application Number:
20240026529
Embodiments of the disclosure provide conformally deposited molybdenum films having reduced resistivity and methods of forming the same. The methods include converting an amorphous silicon layer to a metal layer by thermally soaking the amorphous silicon layer comprising silicon atoms in the presence of a metal compound selected from the group consisting of a molybdenum compound and a tungsten compound until at least a portion of the silicon atoms in the amorphous silicon layer are…
ADVANCED-PACKAGING HIGH-VOLUME-MODE DIGITAL-LITHOGRAPHY-TOOL
Granted: January 25, 2024
Application Number:
20240027896
Exemplary methods of packaging a substrate may include rotationally aligning a substrate to a predetermined angular position. The methods may include transferring the substrate to a metrology station. The methods may include measuring a topology of the substrate at the metrology station. The methods may include applying a first chucking force to the substrate to flatten the substrate. The methods may include generating a mapping of a die pattern on an exposed surface of the substrate.…
METHOD TO REDUCE LINE EDGE ROUGHNESS FOR EUV PHOTORESIST PATTERN
Granted: January 25, 2024
Application Number:
20240027912
Methods of depositing a conformal carbon-containing film on an EUV photoresist to reduce line edge roughness (LER) are described. Exemplary processing methods may include flowing a first precursor over a patterned EUV surface to form a first portion of an initial carbon-containing film on the structure. The methods may include removing a first precursor effluent from the patterned EUV photoresist. A second precursor may then be flowed over the patterned EUV photoresist to react with the…
APPARATUS, SYSTEM AND METHOD FOR ENERGY SPREAD ION BEAM
Granted: January 25, 2024
Application Number:
20240029997
An ion implanter may include an ion source, arranged to generate a continuous ion beam, a DC acceleration system, to accelerate the continuous ion beam, as well as an AC linear accelerator to receive the continuous ion beam and to output a bunched ion beam. The ion implanter may also include an energy spreading electrode assembly, to receive the bunched ion beam and to apply an RF voltage between a plurality of electrodes of the energy spreading electrode assembly, along a local…
RESONATOR, LINEAR ACCELERATOR CONFIGURATION AND ION IMPLANTATION SYSTEM HAVING ROTATING EXCITER
Granted: January 25, 2024
Application Number:
20240032183
An exciter for a high frequency resonator. The exciter may include an exciter coil inner portion, extending along an exciter axis, an exciter coil loop, disposed at a distal end of the exciter coil inner portion. The exciter may also include a drive mechanism, including at least a rotation component to rotate the exciter coil loop around the exciter axis.
METHOD OF DEPOSITING SILICON BASED DIELECTRIC FILM
Granted: January 25, 2024
Application Number:
20240026527
A method of forming a high aspect ratio structure within a 3D NAND structure is provided. The method includes delivering a precursor to a high aspect ratio opening disposed within a multilayer stack having two or more alternating layers. The precursor is selected from the group consisting of a diaminosilane, an aminosilane, and a combination thereof. The method includes delivering an oxygen-containing compound to the high aspect ratio opening. The precursor and the oxygen-containing…
CONFORMAL MOLYBDENUM DEPOSITION
Granted: January 25, 2024
Application Number:
20240026529
Embodiments of the disclosure provide conformally deposited molybdenum films having reduced resistivity and methods of forming the same. The methods include converting an amorphous silicon layer to a metal layer by thermally soaking the amorphous silicon layer comprising silicon atoms in the presence of a metal compound selected from the group consisting of a molybdenum compound and a tungsten compound until at least a portion of the silicon atoms in the amorphous silicon layer are…
ADVANCED-PACKAGING HIGH-VOLUME-MODE DIGITAL-LITHOGRAPHY-TOOL
Granted: January 25, 2024
Application Number:
20240027896
Exemplary methods of packaging a substrate may include rotationally aligning a substrate to a predetermined angular position. The methods may include transferring the substrate to a metrology station. The methods may include measuring a topology of the substrate at the metrology station. The methods may include applying a first chucking force to the substrate to flatten the substrate. The methods may include generating a mapping of a die pattern on an exposed surface of the substrate.…
INTEGRATING STRAIN SiGe CHANNEL PMOS FOR GAA CMOS TECHNOLOGY
Granted: January 11, 2024
Application Number:
20240014214
Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a semiconductor material between source regions and drain regions of the device. The method includes formation of a cladding material on a first material followed by a dry oxidation process resulting rearrangement of the cladding material and first material.
SELECTIVE CAPPING OF CONTACT LAYER FOR CMOS DEVICES
Granted: January 11, 2024
Application Number:
20240014076
A method of forming an electrical contact in a semiconductor structure includes performing a patterning process to form a hard mask on a semiconductor structure comprising a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region, wherein the hard mask covers an exposed surface of the first semiconductor region within the first opening, performing a…
CARBON HARDMASK OPENING USING BORON NITRIDE MASK
Granted: January 11, 2024
Application Number:
20240014039
Exemplary semiconductor processing methods may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include forming a plasma of the oxygen-containing precursor to produce oxygen-containing plasma effluents. The methods may include contacting a substrate housed in the processing region with the oxygen-containing plasma effluents. The substrate may include a boron-and-nitrogen-containing material overlying a…
INTEGRATING STRAIN SiGe CHANNEL PMOS FOR GAA CMOS TECHNOLOGY
Granted: January 11, 2024
Application Number:
20240014214
Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a semiconductor material between source regions and drain regions of the device. The method includes formation of a cladding material on a first material followed by a dry oxidation process resulting rearrangement of the cladding material and first material.
SELECTIVE CAPPING OF CONTACT LAYER FOR CMOS DEVICES
Granted: January 11, 2024
Application Number:
20240014076
A method of forming an electrical contact in a semiconductor structure includes performing a patterning process to form a hard mask on a semiconductor structure comprising a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region, wherein the hard mask covers an exposed surface of the first semiconductor region within the first opening, performing a…
CARBON HARDMASK OPENING USING BORON NITRIDE MASK
Granted: January 11, 2024
Application Number:
20240014039
Exemplary semiconductor processing methods may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include forming a plasma of the oxygen-containing precursor to produce oxygen-containing plasma effluents. The methods may include contacting a substrate housed in the processing region with the oxygen-containing plasma effluents. The substrate may include a boron-and-nitrogen-containing material overlying a…
COMPOSITE BARRIER LAYERS
Granted: January 4, 2024
Application Number:
20240006235
Described are methods for forming ruthenium doped niobium nitride barrier layers. The doped barrier layer provides improved adhesion at a thickness of less than about 15 ?. In some embodiments, the doped barrier layers disclosed herein provide improved barrier properties including a lower nitrogen content, a higher ruthenium content, better coverage, thinner layers, or lower line resistance
CO-DOPING TO CONTROL WET ETCH RATE OF FCVD OXIDE LAYERS
Granted: January 4, 2024
Application Number:
20240006158
A method for reducing a wet etch rate of flowable chemical vapor deposition (FCVD) oxide layers in a semiconductor wafer, the method including performing a plasma doping operation on the semiconductor wafer using a primary dopant gas and a diluent gas adapted to reduce a wet etch rate of the FCVD oxide layer, wherein the dopant gas and the diluent gas are supplied by a gas source of a plasma doping system, wherein the diluent gas is provided in an amount of 0.01%-5% by volume of the…
INTEGRATED METHOD AND TOOL FOR HIGH QUALITY SELECTIVE SILICON NITRIDE DEPOSITION
Granted: December 28, 2023
Application Number:
20230420232
Methods of manufacturing memory devices are provided. The method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; exposing the top surface of the film stack to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying…
