METHODS OF FORMING SEMICONDUCTOR STRUCTURES
Granted: May 9, 2024
Application Number:
20240154018
Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition…
PROCESS CHAMBER WITH PRESSURE CHARGING AND PULSING CAPABILITY
Granted: May 9, 2024
Application Number:
20240153790
Processing chambers including at least one gas reservoir connected to and in fluid communication with the lid through a fast-switching valve and a gas reservoir line are described. Processing methods, for example, etching methods, using the processing chambers are also described.
PLASMA ASSISTED DAMAGE ENGINEERING DURING ION IMPLANTATION
Granted: May 9, 2024
Application Number:
20240153775
A method of method of treating a semiconductor substrate. The method may include, in a beamline ion implanter, exposing a substrate surface of the semiconductor substrate to a plasma clean and exposing the substrate surface to a hydrogen treatment from a plasma source. The method may further include, in the beamline ion implanter, exposing the substrate to an implant process after formation of the hydrogen passivation, wherein the substrate is maintained under vacuum over a process…
MULTIPROCESS SUBSTRATE TREATMENT FOR ENHANCED SUBSTRATE DOPING
Granted: May 9, 2024
Application Number:
20240153774
A method of doping a substrate may include exposing a substrate surface of the semiconductor substrate to a plasma clean, performing a deposition of a dopant layer on the substrate surface using a plasma source, after the plasma clean, the dopant layer comprising a dopant element; and exposing the substrate to an implant process when the dopant layer is disposed on the substrate surface, wherein the implant process introduces an ion species comprising the dopant element into the…
DYNAMIC PRESSURE CONTROL FOR PROCESSING CHAMBERS IMPLEMENTING REAL-TIME LEARNING
Granted: May 9, 2024
Application Number:
20240153750
System and methods of improving dynamic pressure response during recipe step transitions. An exemplary method may include changing at least one of a plurality of recipe parameters in accordance with a processing recipe while running the processing recipe on a semiconductor substrate in a processing chamber. The method may further include measuring a pressure response in the processing chamber responsive to the changing of the at least one of the plurality of recipe parameters, and…
PRECISION IN STEREOSCOPIC MEASUREMENTS USING A PRE-DEPOSITION LAYER
Granted: May 9, 2024
Application Number:
20240153738
A method of determining the depth of a hole milled into a first region of a sample, the method comprising: positioning the sample in a processing chamber having a charged particle beam column; depositing material directly over a top surface of the sample in a second region of the sample adjacent to the first region; milling the hole in the first region of the sample using a charged particle beam generated by the charged particle beam column, wherein the hole abuts the material deposited…
VOLUME FILLING CASSETTE FOR LOAD LOCK
Granted: May 9, 2024
Application Number:
20240153733
An ion implantation system including an ion source for generating an ion beam, an end station containing a platen for supporting a substrate to be implanted by the ion beam, and a load lock disposed adjacent the end station and adapted to transfer substrates between an external environment and the end station. The load lock may include a transfer chamber having a hollow interior, a first isolation door affixed to a first side of the transfer chamber and openable to the external…
ELECTRICAL IMPEDANCE MEASUREMENT USING AN ELECTRON BEAM
Granted: May 9, 2024
Application Number:
20240151669
A method for evaluating an impedance related value of a structure of a sample, the method includes: (i) performing a first illumination iteration that includes charging the structure with an illumination iteration charge; (ii) performing a second illumination iteration that includes imaging the structure to provide an image of the structure; a value of the illumination iteration charge and a value of a time difference between step (i) and step (ii) are determined to introduce a…
FARADAY FACEPLATE
Granted: May 2, 2024
Application Number:
20240145252
Exemplary semiconductor processing chamber faceplates may include a body having a first surface and a second surface opposite the first surface. The body may define a plurality of apertures that extend through one or both of the first surface and the second surface. The faceplates may include a heater disposed within an interior of the body. The faceplates may include a first RF mesh disposed between the heater and the first surface. The faceplates may include a second RF mesh disposed…
LIGHT ABSORBING BARRIER FOR LED FABRICATION PROCESSES
Granted: May 2, 2024
Application Number:
20240145623
Exemplary semiconductor structures may include a plurality of LED structures and a backplane layer. Exemplary semiconductor structures may also include a light barrier region positioned between the LED structures and the backplane layer. The light barrier region may be operable to absorb light at wavelengths shorter than or about 300 nm and transmit light at wavelengths greater than or about 350.
SEMICONDUCTOR FILM PLATING PERIMETER MAPPING AND COMPENSATION
Granted: May 2, 2024
Application Number:
20240145251
Conditions at the perimeter of the wafer may be characterized and used to adjust current stolen by the weir thief electrodes during a plating process to generate more uniform film thicknesses. An electrode may be positioned in a plating chamber near the periphery of the wafer as the wafer rotates. To characterize the electrical contacts on the seal, a wafer with a seed layer may be loaded into the plating chamber, and a constant current may be driven through the electrode into the…
OXIDATION ENHANCED DOPING
Granted: May 2, 2024
Application Number:
20240145246
Embodiments of the present technology include semiconductor processing methods. The methods may include providing a silicon-containing precursor and a dopant precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the semiconductor processing chamber. A silicon-containing material may be formed on the substrate. The methods may include contacting the silicon-containing material with the silicon-containing precursor and the dopant…
ALUMINUM OXIDE CARBON HYBRID HARDMASKS AND METHODS FOR MAKING THE SAME
Granted: May 2, 2024
Application Number:
20240145245
Embodiments of the present disclosure generally relate to methods for enhancing carbon hardmask to have improved etching selectivity and profile control. In some embodiments, a method of treating a carbon hardmask layer is provided and includes positioning a workpiece within a process region of a processing chamber, where the workpiece has a carbon hardmask layer disposed on or over an underlying layer, and treating the carbon hardmask layer by exposing the workpiece to a sequential…
LOW TEMPERATURE CO-FLOW EPITAXIAL DEPOSITION PROCESS
Granted: May 2, 2024
Application Number:
20240145240
Methods for selectively depositing an epitaxial layer are provided. In some implementations, the selective epitaxial deposition process includes providing the co-flow of chlorosilane precursors with at least one of an antimony-containing precursor and a phosphorous-containing precursor. The method utilizes co-flowing of multiple chlorosilane precursors to enable combination of silicon and at least one of phosphorous and antimony in the same matrix using a low-temperature selective…
SEMICONDUCTOR CLEANING USING PLASMA-FREE PRECURSORS
Granted: May 2, 2024
Application Number:
20240145230
Exemplary semiconductor processing methods may include providing one or more deposition precursors to a semiconductor processing chamber. A substrate may be disposed within a processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate and on one or more components of the semiconductor processing chamber. The methods may include providing a fluorine-containing precursor to the processing region. The…
ALUMINUM OXIDE CARBON HYBRID HARDMASKS AND METHODS FOR MAKING THE SAME
Granted: May 2, 2024
Application Number:
20240142870
Embodiments of the present disclosure generally relate to methods for enhancing carbon hardmask to have improved etching selectivity and profile control. In some embodiments, a method of treating a carbon hardmask layer is provided and includes positioning a workpiece within a process region of a processing chamber, where the workpiece has a carbon hardmask layer disposed on or over an underlying layer, and treating the carbon hardmask layer by exposing the workpiece to a sequential…
REFLECTIVE DISPLAY DEVICES AND COMPONENTS
Granted: May 2, 2024
Application Number:
20240142767
Exemplary reflective display components are described. These reflective display components may include a microwell layer having a first and a second quantum dot well that each include a plurality of nanoparticles configured to emit a color of light. The microwell layer further has a third well. The reflective display components further include an electrowetting layer positioned above the microwell layer, where the electrowetting layer is operable to independently adjust an intensity of…
DIELECTRIC FILM SURFACE RESTORATION WITH REDUCTIVE PLASMA
Granted: May 2, 2024
Application Number:
20240141497
Methods for forming an EUV photoresist hard mask are provided. The method includes treating a metal-rich layer on a substrate with a reductive plasma to form a metallic surface on the metal-rich layer, the metal-rich layer having a top portion comprising a metal oxide layer. The metal-rich layer comprises one or more of tin (Sn), indium (In), gallium (Ga), zinc (Zn), tellurium (Te), antimony (Sb), nickel (Ni), titanium (Ti), aluminum (Al), tantalum (Ta), bismuth (Bi), and lead (Pb).
SEMICONDUCTOR MANUFACTURING SUSCEPTOR POCKET EDGE FOR PROCESS IMPROVEMENT
Granted: May 2, 2024
Application Number:
20240141492
Susceptor assemblies having a susceptor base with a plurality of pockets formed in a surface thereof are described. Each of the pockets has a pocket edge angle in the range of 30 to 75° and a pocket edge radius in the range of 0.40±0.05 mm to 1.20 mm±0.05 mm. The pockets have a raised central region and an outer region that is deeper than the raised central region, relative to the surface of the surface of the susceptor base.
PROCESS CHAMBER WITH REFLECTOR
Granted: April 25, 2024
Application Number:
20240134151
A reflector and processing chamber having the same are described herein. In one example, a reflector is provided that includes cylindrical body, a cooling channel, and a reflective coating. The cylindrical body has an upper surface and a lower surface. The lower surface has a plurality of concave reflector structures disposed around a centerline of the cylindrical body. The cooling channel disposed in or on the cylindrical body. The reflective coating is disposed on the plurality of…
