Multi-input IIR filter with error feedback
Granted: February 4, 2014
Patent Number:
8645446
Methods and systems for multi-input IIR filters with error feedback are disclosed. By using multiple-inputs to generate multiple outputs during each iteration, a multi-input IIR filter in accordance with the present invention has greatly increased throughput. Furthermore, the addition of a multi-variable error feedback unit in accordance with the present invention in a multiple-input IIR filter can greatly increase the accuracy of the multi-variable IIR Filter.
System-on-chip queue status power management
Granted: January 28, 2014
Patent Number:
8639862
A system and method are provided for using queue status to manage power in a system-on-chip (SoC). Messages to be processed are accepted in an SoC with a plurality of selectively enabled processors, and queued. The message traffic can be from an external source via an input/output (IO) interface, or intra-SoC messages between processors. The number of queued messages is monitored and, in response to the number of queued messages exceeding a subscription threshold, one or more processors…
Adaptive narrowband interference prediction circuit and method
Granted: January 28, 2014
Patent Number:
8638892
An input signal that includes narrowband interference is spectrally enhanced by an adaptive circuit that supplies as output signal(s), portion(s) of NBI at one or more frequencies that change adaptively. The output signal(s) are used in one or more tone predictor(s) to generate, based on prior values of the NBI portion, one or more predicted tone signals that are subtracted from a received signal containing the NBI, and the result is used in the normal manner, e.g. decoded. The adaptive…
System-on-chip with management module for controlling processor core internal voltages
Granted: January 21, 2014
Patent Number:
8635470
A system and method are provided for a system-on-chip (SoC) management module to monitor and dynamically control processor core operating voltages. An SoC is provided with a plurality of processor cores, a plurality of voltage regulators, an internal management module, and at least one temperature sensor. The management module compares monitored temperatures to threshold values, and in response generates voltage commands. The management module sends the voltage commands to the voltage…
Shadow latch
Granted: December 31, 2013
Patent Number:
8618856
A latch device is provided with a driver and a shadow latch. The driver has an input to accept a binary driver input signal, an input to accept a clock signal, and an input to accept a shadow-Q signal. The driver has an output to supply a binary Q signal equal to the inverse of the driver input signal, in response to the driver input signal, the shadow-Q signal, and the clock signal. The shadow latch has an input to accept the driver input signal, and an input to accept the clock signal.…
System and method for deferred data downloading
Granted: December 24, 2013
Patent Number:
8615548
A system and method are provided for downloading data to a client device by deferral to an on-line storage device. A client sends a login request to a network-connected remote service device, and receives a remote service identification (ID) from the remote service device. The client sends a token request message, with the remote service ID, to a network-connected on-line storage device, and receives a first token identification (ID) associated with a first session and an on-line storage…
Method for converting a single channel hardware module into a multi-channel module
Granted: December 10, 2013
Patent Number:
8607181
A system and method are provided for automatically converting a hardware abstraction language representation of a single-channel hardware module into a hardware abstraction language representation of a multi-channel module. Initially, a hardware abstraction language representation of a single channel hardware module is provided having an input port, output port, and a register. The method defines a number of channels and establishes a context switching memory. Commands are created for…
System-on-chip with dynamic memory module switching
Granted: December 10, 2013
Patent Number:
8607023
A system and method are provided for using a system-on-chip (SoC) memory manager to dynamically shutdown and restart an off-chip memory module. After determining that a memory switch is to be enacted, an SoC memory switching core asserts a hold on processor operations. The memory switching core transfers data from a source memory module to a destination memory module. In a shutdown operation, data is transferred from a first memory module source to an external second memory module…
Pseudo single-phase flip-flop (PSP-FF)
Granted: December 10, 2013
Patent Number:
8604854
Disclosed herein is a pseudo single-phase flip-flop. The master section includes a pre-dissipation stage and a first keeper. The pre-dissipation stage discharges the first keeper to the mDb second binary value, and selectively charges the first keeper with the mDb first binary value in the master pass mode. The pre-dissipation stage selectively prevents the first keeper from charging to the mDb first binary value in response to one of the clock phases. The slave section includes a…
Inverse multiplexing using transcoding and frame alignment markers
Granted: November 26, 2013
Patent Number:
8594125
A system and method are provided for framing messages in a data streams encoded with redundant information for transmission and recovering the messages at a receiver. The transmission method accepts an energy waveform representing N words at a first bit rate, encoded with redundant information, where each word includes P number of bits. The N words are transformed, creating N transcoded words, where each transcoded word includes Q number of bits, and where Q<P. The N transcoded words…
Confirmation of presence of narrowband interference by harmonic analysis
Granted: November 12, 2013
Patent Number:
8582633
One or more processing units confirm existence of narrow band interference in a signal by using an estimate f of the frequency, to check for one or more harmonics. In illustrative embodiments, the estimate f is automatically identified as a second harmonic if a predetermined criterion is satisfied by the signal (in the frequency domain) at either of two frequencies namely (A) frequency f/2 and (B) frequency (M?f)/2 and whichever of these two frequencies is stronger is identified as the…
Multistage latch-based isolation cell
Granted: November 5, 2013
Patent Number:
8575984
A multistage latch-based isolation cell is provided. The isolation cell includes a latch to receive a first binary signal and an enable signal. The latch initially supplies a second binary signal with an unknown value in response to the enable port receiving an enable signal having a first polarity value, and subsequent to receiving the first binary signal with a first value, supplying the second binary signal with the first value. The isolation cell includes a delay device to receive…
Multichannel data conversion into packets
Granted: October 29, 2013
Patent Number:
8571062
A system and method are provided for converting multichannel serial data streams into packets. The method accepts a plurality of serial data streams in a corresponding plurality of channels. In a time domain multiplexed (TDM) fashion, groups with an undetermined number of data bits are packed from each data stream, into an associated channel segment queue, where each segment includes a predetermined number of bits. In a TDM fashion, segments are loaded into an associated channel payload…
Clock generation for N.5 modulus divider
Granted: October 15, 2013
Patent Number:
8558575
A system is provided for generating an output clock used for N.5 modulus division. An edge-slip circuit accepts a modulus count, a divisor select signal, and a clock signal having a frequency greater than a modulus count frequency. The edge-slip circuit also has an input to accept an output clock signal, and an output to supply a clock slip signal (NE). An exclusive-or (XOR) has an input to accept a buffered clock signal (NF) and the clock slip signal (NE). The XOR has an output to…
Frequency generation using a single reference clock and a primitive ratio of integers
Granted: October 8, 2013
Patent Number:
8554815
A system and method are provided for synthesizing signal frequencies using a single reference clock and a primitive ratio of integers. The method accepts a plurality (k) of reference frequency values (fri), where 1?i?k, associated with a corresponding plurality of synthesized frequency values (foi). For each synthesized frequency value, a raw ratio of integers Nprawi and Dprawi is calculated, such that: f o i = Np raw i Dp raw i × f r i . A greatest common divisor…
System and method for packet and time division multiplexed transport
Granted: September 24, 2013
Patent Number:
8542694
A system and method are presented for providing packet and time division multiplex (TDM) services in a data communication interface. The method accepts packets at a first rate over a packet interface, and transfers time-sensitive data in the packets as packet data units (PDUs) having a smaller number of bits than a packet and a second rate, faster than the first rate. The method transforms the PDUs into frames in a first TDM protocol. Typically, the PDUs are transformed into units having…
Frequency optimization using useful skew timing
Granted: September 17, 2013
Patent Number:
8539413
A circuit analysis tool is provided for optimizing circuit clock operating frequency using useful skew timing analysis. The instructions supply clock signal with an optimized operating frequency. A first gate signal input slack time is determined with respect to the clock signal to the first gate. If the first gate signal input has a negative slack time, a delay is added to the first clock signal. A second gate signal input slack time is determined with respect to the clock signal to the…
System and method for process, voltage, temperature (PVT) stable differential amplifier transfer function
Granted: September 10, 2013
Patent Number:
8531241
A method is provided for process, voltage, temperature (PVT) stable transfer function calibration in a differential amplifier. The gain resistors of a differential amplifier are initially selected to achieve a flat amplitude transfer function in the first frequency band. After calibration, the degeneration capacitor is connected and tuned until a peaked amplitude transfer function is measured, which is resistant to variations in PVT. As an alternative, the degeneration capacitor is not…
System and method for in-situ inspection during metallurgical cross-sectioning
Granted: August 13, 2013
Patent Number:
8506355
A system and method are provided for in-situ inspection optical inspection during a parallel polishing process. The method provides a polishing device with a spindle bit for holding a metallurgical sample, and a rotatable wheel having an inner diameter with a top surface for accepting a polishing compound and a transparent outer diameter. An optical system underlies the wheel outer diameter for recording images of the metallurgical sample. The method polishes the metallurgical sample…
System and method for attached storage stacking
Granted: July 30, 2013
Patent Number:
8499012
A system and method are provided for stacking storage drives in a network attached storage (NAS) system. The method provides a NAS stacking network including at least a first and second stackable building block (SBB), where each SBB includes a head, with an embedded processor and storage application, and a storage drive including client files. The method connects a first interface of the first SBB to a client computer device via a LAN switch, and connects a second interface of the first…
