MICROCONTROLLER INFORMATION EXTRACTION SYSTEM AND METHOD
Granted: January 14, 2010
Application Number:
20100011250
A system for debugging a device under test may include a processor register with a program count and a debug program register that receives the program count upon execution of an instruction by a processor. In one implementation, a microcontroller under test by a debugger is accessed using a serial interface, such as a JTAG interface. The interface can communicate directly with a debug register to retrieve program count values, both when the microcontroller is halted and when it is…
Differential Sense Amplifier
Granted: January 14, 2010
Application Number:
20100008159
A differential sense amplifier can perform data sensing using a very low supply voltage.
Mode Switching RC Network
Granted: January 7, 2010
Application Number:
20100001812
Various embodiments include apparatus, systems, and methods having a conductive contact configured to couple to a resistor-capacitor (RC) network, a device unit coupled to the conductive contact, and a mode switching unit to change a characteristic of a signal at the conductive contact based at least in part on an RC time constant of the RC network. The mode switching unit may switch the device unit between a first operating mode and a second operating mode based on a signal level of the…
MEMORY ADDRESS OBFUSCATION
Granted: December 31, 2009
Application Number:
20090327709
Apparatus, systems, and methods may operate to provide, to a memory device, an obfuscated clear-page address derived from a clear-page address that is not the same as a key-page address and/or providing, to the memory device, an obfuscated key-page address derived from the key-page address when the obfuscated clear-page address is the same as the key-page address. Additional apparatus, systems, and methods are disclosed.
PACKAGED PRODUCTS, INCLUDING STACKED PACKAGE MODULES, AND METHODS OF FORMING SAME
Granted: December 10, 2009
Application Number:
20090302449
An apparatus and a method for packaging semiconductor devices. The apparatus is a three-dimensional electronic package comprising one or more electronic components, a plurality of electrical contact pads, and a plurality of electrically conductive three-dimensional plugs formed through an encapsulant. Specific ones of the plurality of electrical contact pads are electrically coupled to the one or more electronic components on an uppermost surface of the plurality of electrical contact…
ROM ARRAY WITH SHARED BIT-LINES
Granted: December 10, 2009
Application Number:
20090303769
Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits.
APPARATUS AND METHODS FOR A HIGH-VOLTAGE LATCH
Granted: December 3, 2009
Application Number:
20090295447
Some embodiments include a device having storage node and a latch circuit coupled to the storage node to latch data provided to the storage node during one of a first mode and a second mode of the device. The latch circuit includes a first transistor, a second transistor, and a third transistor coupled between a first voltage node and a second voltage node. The third transistor is configured to selectively turn on and off in the first and second modes. Other embodiments are described.
Differential Varactor
Granted: November 26, 2009
Application Number:
20090289329
A high-Q differential varactor includes reduced inner spacing dimensions between differential fingers.
OSCILLATOR FOR GENERATING DIFFERENT OSCILLATIONS
Granted: November 26, 2009
Application Number:
20090289727
An oscillator is provided that includes a first oscillation generating device for generating an oscillation in response to an excitation signal, whereby the first oscillation generating device has a first terminal and a second terminal; a second oscillation generating device for generating an oscillation in response to an excitation signal, whereby the second oscillation generating device has a third terminal and a fourth terminal; an excitation device, which is formed in a first mode to…
SELECTABLE DELAY PULSE GENERATOR
Granted: November 19, 2009
Application Number:
20090284296
A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and…
Addressable Memory Array
Granted: November 12, 2009
Application Number:
20090279361
This document discloses non-volatile memory cells and methods of manufacturing the same. The memory arrays are byte, word, and/or page addressable without using a byte select transistor. The byte select transistor is eliminated by using the well, memory transistor control gates, and select transistor gates to selectively program a byte, word, or page.
NON-VOLATILE MEMORY CELL
Granted: November 5, 2009
Application Number:
20090273015
This document discloses non-volatile memory cells and methods of manufacturing the same. The non-volatile memory cells are self-aligned and have a reduced tunnel window area that is within an active region of a substrate. The tunnel window area can be reduced using mask openings without optical proximity correction that define tunnels having one or more curvatures.
DESCRIPTOR INTEGRITY CHECKING IN A DMA CONTROLLER
Granted: October 29, 2009
Application Number:
20090271536
The present invention relates to a Direct Memory Access controller that, in an embodiment, executes I/O descriptors conditionally. A linked list item contains a checksum computed on the descriptor fields. When the linked list item is fetched, the checksum is computed on the descriptor. If both checksums are equal, the linked list item is considered valid and the descriptor is executed. At the end of a DMA I/O, the next descriptor in the linked list is fetched. When the checksum fails,…
CRYPTOGRAPHIC AUTHENTICATION APPARATUS, SYSTEMS AND METHODS
Granted: October 22, 2009
Application Number:
20090265411
Apparatus, systems, and methods send an interrogation command from an interrogation and timing apparatus to a timed identification (TID) apparatus. The TID apparatus receives the interrogation command, performs a series of logical operations to calculate a response, and returns the response within a maximum length of time established by the interrogation and timing apparatus. The interrogation and timing apparatus confirms that the length of time between sending the interrogation command…
Randomizing Current Consumption in Memory Devices
Granted: October 15, 2009
Application Number:
20090257295
In some implementations, a memory device includes a plurality of memory cells, each memory cell storing a plurality of data bits; an input/output interface that is configured to, in response to receiving a read signal and an address value that identifies a specific memory cell in the plurality of memory cells, output a plurality of data bits corresponding to the identified specific memory cell; and a delay controller that is configured to delay the outputting to the input/output…
Semiconductor array and method for manufacturing a semiconductor array
Granted: October 15, 2009
Application Number:
20090258472
Method for manufacturing a semiconductor array, in which a conductive substrate (100), a component region (400), and an insulation layer (200), isolating the component region (400) from the conductive substrate (100), are formed, a trench (700) is etched in the component region (400) as far as the insulation layer (200), then the trench (700) is etched further as far as the conductive substrate (100), the walls (701) of the trench (700) are formed with an insulation material (710),…
METHOD FOR PROVIDING A NANOSCALE, HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) ON INSULATOR
Granted: October 15, 2009
Application Number:
20090258478
Various embodiments include forming a silicon-germanium layer over a substrate of a device; forming a layer in the silicon-germanium layer, the layer including at least one of boron and carbon; and forming a silicon layer over the silicon-germanium layer. Additional embodiments are described.
RANDOM NUMBER GENERATOR IN A BATTERY PACK
Granted: October 1, 2009
Application Number:
20090243539
Apparatus, method and computer program product are provided for battery management. In one implementation, a method of communication provided. The method includes enabling determining when a battery pack is coupled to a device, the battery pack including a battery management system. The method also includes generating a random number at the battery management system, the battery management system including battery monitoring circuitry, a processor, memory and a random number generator.…
METALLIC NANOCRYSTAL PATTERNING
Granted: October 1, 2009
Application Number:
20090246510
A device and method include forming a mask on a substrate supporting a plurality of metallic nanocrystals such that a portion of the metallic nanocrystals is exposed. Protective shells are formed about the exposed metallic nanocrystals. Unprotected metallic nanocrystals are removed.
ACCESSING SEQUENTIAL DATA IN A MICROCONTROLLER
Granted: October 1, 2009
Application Number:
20090249136
System and methods transfer data over a microcontroller system test interface. The system can read data from and write data to microcontroller system memory using the described method. The method provides for the efficient transfer of data, minimizing redundancies and overhead present in conventional microcontroller test system protocols.
