ACCESSING SEQUENTIAL DATA IN A MICROCONTROLLER
Granted: October 1, 2009
Application Number:
20090249136
System and methods transfer data over a microcontroller system test interface. The system can read data from and write data to microcontroller system memory using the described method. The method provides for the efficient transfer of data, minimizing redundancies and overhead present in conventional microcontroller test system protocols.
CIRCUITS TO DELAY SIGNALS FROM A MEMORY DEVICE
Granted: September 24, 2009
Application Number:
20090238016
Various embodiments include method and apparatus for receiving a clock signal, determining a number of delay elements based on a relationship between the clock signal and a delayed feedback signal generated based on the clock signal, calculating an amount of time corresponding to the number of delay elements, and delaying a control signal by the amount of time to generate an additional clock signal, the control signal having a frequency higher than a frequency of the clock signal. Other…
APPARATUS FOR DETECTING A USB HOST
Granted: September 24, 2009
Application Number:
20090240843
A multi-interface integrated circuit (IC) comprises a plurality of transistors, and a level detection block. At least one transistor of the plurality of transistors is in communication with a first terminal and either a first or a second lead of the multi-interface IC, and at least one of the plurality of transistors is in communication with the first terminal, a second terminal and either the first or a second lead of the multi-interface IC. The level detection block is in communication…
Cyclic pipeline analog-to-digital converter
Granted: September 10, 2009
Application Number:
20090224951
Some embodiments include apparatus and methods having a first module with a capacitor network configured to receive a sample of an analog input signal and an amplifier configured to couple to the capacitor network in a plurality of arrangements to successively generate a plurality of residue signals at an amplifier output node of the amplifier without resetting the amplifier between generation of least two of the plurality of residue signals, and a second module configured to generate a…
Wafer-Level Integrated Circuit Package with Top and Bottom Side Electrical Connections
Granted: September 3, 2009
Application Number:
20090218698
A wafer-level, batch processed, die-sized integrated circuit (IC) package with both top and bottom side electrical connections is disclosed. In one aspect, a number of bonding wires can be attached to bond pads on the top side (active circuit side) of an IC wafer. Trenches can be formed in the wafer at scribe regions and the bonding wires can extend through the trench. The trench can be filled with coating material. The bonding wires can be partially exposed on the top and/or bottom…
APPARATUS TO IMPROVE BANDWIDTH FOR CIRCUITS HAVING MULTIPLE MEMORY CONTROLLERS
Granted: August 27, 2009
Application Number:
20090216926
An apparatus for improving bandwidth for circuits having a plurality of memory controllers employing a first memory controller, a second memory controller, a first busy read output signal circuit, a first busy write output signal circuit, a second busy read output signal circuit, and a second busy write output signal circuit. The first busy read output signal indicates when the first memory controller releases the address bus for a next external access subsequent to a read access to the…
METHOD AND SYSTEM FOR CREATING SELF-ALIGNED TWIN WELLS WITH CO-PLANAR SURFACES IN A SEMICONDUCTOR DEVICE
Granted: August 20, 2009
Application Number:
20090206452
A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the…
FABRICATING LOW COST SOLDER BUMPS ON INTEGRATED CIRCUIT WAFERS
Granted: August 20, 2009
Application Number:
20090206480
A low cost method of forming solder bumps on an integrated circuit (IC) wafer includes depositing solder directly onto stud bumps formed on bond pads of the IC wafer. In some implementations, stud bumps are formed on the IC wafer by performing wire ball-bonding onto metal bond pads of the wafer. Photodefinable solder mask material is applied to the wafer and cured. The photodefinable solder mask material is exposed to form open solder mask areas at the metal bond pad areas. Solder paste…
ERROR DETECTING/CORRECTING SCHEME FOR MEMORIES
Granted: August 20, 2009
Application Number:
20090210774
A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR…
METHOD AND APPARATUS FOR ESD PROTECTION
Granted: August 13, 2009
Application Number:
20090201615
A technique that minimizes false triggering of an electrostatic discharge (ESD) protection circuit is disclosed. In an embodiment, the resistor-capacitor (RC) time constant of an ESD trigger element is reduced during normal operation minimizing the risk of false triggering. Circuit layout area is saved without the need of a timeout circuit associated with releasing a device maintaining a trigger state (i.e., a trigger latch). A RC time constant for triggering is set in an operational…
NON-VOLATILE MEMORY CELL
Granted: August 6, 2009
Application Number:
20090194804
Disclosed herein are non-volatile cells and methods of manufacturing the same. The nonvolatile memory cells include a high voltage device, a low voltage device, and a memory cell formed on a semiconductor substrate. The high voltage device, low voltage device, and memory cell are all self-aligned by using the gates associated with each of the devices as a mask during formation of the respective sources and drains.
GETTERING LAYER ON SUBSTRATE
Granted: July 30, 2009
Application Number:
20090189159
Disclosed herein are devices, methods and systems for implementing gettering layers. Devices including gettering layers can be implemented such that a gettering layer doped with carbon, boron, fluorine or any other appropriate impurity is formed on a semiconductor substrate, a device layer is formed on the gettering layer, and a device region is formed in the device layer having a depth that maintains a distance in the device layer between the gettering layer and the device region.
Data Security Including Real-Time Key Generation
Granted: July 23, 2009
Application Number:
20090187770
Methods for providing data security are described. A security device (10) and a plug-in device (30) work in conjunction to enable encryption and decryption of data. A secret is stored by one of the security device (10) or the plug-in device (30). While the secret is required for constructing a key, the key cannot be constructed from the secret alone. Unauthorized devices or users are thereby prevented from accessing the key.
Modular Reduction Using a Special Form of the Modulus
Granted: July 16, 2009
Application Number:
20090180609
A special form of a modulus and a modified Barrett reduction method are used to perform modular arithmetic in a cryptographic system. The modified Barrett reduction is a method of reducing a number modulo another number without the use of any division. By pre-computing static values used in the Barrett reduction method and by using a special form of the modulus, the calculation of reducing a number modulo another number can be reduced. This can result in a decrease in computation time,…
REPRESENTATION CHANGE OF A POINT ON AN ELLIPTIC CURVE
Granted: July 16, 2009
Application Number:
20090180611
An elliptic curve cryptographic system where point coordinates are transformed from a first coordinate system to a second coordinate system. The transformed coordinates are processed by field operations, which have been modified for operating on the transformed point coordinates. In some implementations, the point coordinates are transformed from an affine coordinate system to a projective coordinate system using a non-random value for the projective coordinate. In some implementations,…
Method of increasing reliability of packaged semiconductor integrated circuit dice
Granted: July 2, 2009
Application Number:
20090166898
A method increases a reliability of packaged semiconductor integrated circuit dice by identifying one or more dice on a wafer having failed an electrical test. One or more failed dice are added to a character map. A first tier of buffer dice is added to the initial character map adjacent to each die on the character map. Both the failed dice and the first tier of buffer dice are indicated or marked, such as by inking, thereby indicating dice not requiring packaging. A wafer may include…
CIRCUIT TO CONTROL VOLTAGE RAMP RATE
Granted: July 2, 2009
Application Number:
20090168586
A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling…
Semiconductor array and method for manufacturing a semiconductor array
Granted: June 25, 2009
Application Number:
20090160009
Semiconductor array and method for manufacturing a semiconductor array, wherein a conductive substrate (100), an element region (400), and an insulation layer (200), isolating the element region (400) from the conductive substrate (100), are formed, a trench (700) is etched in the element region (400) as far as the insulation layer (200), the trench (700) is etched further in the insulation layer (200) as far as the conductive substrate (100), and within the trench (700), the…
DYNAMIC COLUMN REDUNDANCY REPLACEMENT
Granted: June 25, 2009
Application Number:
20090161429
A dynamic column redundancy replacement system for programming and reading a non-volatile memory system includes an input data replacement logic block and an output data replacement logic block. A column redundancy match logic block compares a user address to latched fuse addresses of bad columns and identifies address matches to facilitate the replacement of bits from defective memory cells with replacement redundancy bits. For a program mode of operation, a multi-bit data program…
FORMATION AND APPLICATIONS OF HIGH-QUALITY EPITAXIAL FILMS
Granted: June 18, 2009
Application Number:
20090151623
A method and system for forming high-quality epitaxial films. In one embodiment, the method includes cleaning a substrate, reducing adsorbed moisture on the substrate in a predefined temperature and predefined oxygen level atmosphere, and removing native oxide from the substrate. The method also includes prebaking the substrate and growing an epitaxial layer doped with an impurity, wherein the impurity has a nano-impurity profile.
