CURRENT COMPENSATION FOR DIGITAL-TO-ANALOG CONVERTER
Granted: June 18, 2009
Application Number:
20090153380
A current compensation circuit and an optimized current compensation circuit are disclosed for a Parallel Resistors Architecture (PRA) digital-to-analog converter (DAC). The circuits are used to balance code dependent current consumption of the PRA-DAC.
Redundant Bit Patterns for Column Defects Coding
Granted: June 18, 2009
Application Number:
20090158084
Techniques for coding and decoding redundant coding for column defects cartography. Defective cell groups identified in a memory array are redundantly encoded with a different bit pattern than the bit pattern used for functional cell groups. The identified defective cell groups are repaired using redundant cell groups in the memory array. The defective cell groups are later re-identified by checking the redundant bit pattern encoded in the cell groups. If new defective cell groups are…
Low voltage charge pump
Granted: June 18, 2009
Application Number:
20090153232
A single pump stage of a multi-stage charge pump couples a first low-voltage NMOS transistor in series with a first low-voltage PMOS transistor between charge transfer capacitors. A second low-voltage NMOS transistor is coupled between the gate and the source of the first NMOS transistor. A second low-voltage PMOS transistor is coupled between the gate and the source of the first PMOS transistor. Respective boost voltages are applied to gates of the first NMOS transistor and the second…
SECURE CONNECTOR GRID ARRAY PACKAGE
Granted: June 11, 2009
Application Number:
20090146267
Methods, systems, IC packages, and electrical devices for providing data security for ICs. A substrate-on-substrate connector grid array package with an electrical shield can protect sensitive information in a secure IC from being accessed by physical attacks. A current flow in the electrical shield can be monitored for disturbances which can indicate an attack on the IC package.
Secure Software Download
Granted: June 11, 2009
Application Number:
20090150681
Software can be downloaded securely using a multi-encryption method, where the decryption is completed when the software is executed. In one aspect, a multi-encrypted data item is received. One or more of the encryptions on the multi-encrypted data item is decrypted, yielding a partially decrypted data item. The partially decrypted data item is stored in a reserved portion of a storage medium. The partially decrypted data item is fetched from the storage medium and decrypted to yield the…
MEMORY DEVICE HAVING SMALL ARRAY AREA
Granted: June 4, 2009
Application Number:
20090141554
Memory arrays can be implemented including word lines connected to memory transistors and corresponding select transistors. Each memory transistor is also connected to an array select transistor. Each select transistor is also connected to a bit line. The memory transistors are arranged such that they define bytes of data. A well line is connected to each portion of the semiconductor substrate that defines an array of bytes.
SPHERICAL ANTENNA
Granted: May 14, 2009
Application Number:
20090121965
An antenna comprises a first circular coil, a second circular coil, and a third circular coil, and a housing unit including a sending/receiving interrogator chip. The first, second, and third coil are each connected to the housing unit at two points on each of the first, second, and third coil, and the first, second, and third coil are connected substantially in parallel.
MEMORY DEVICE
Granted: May 7, 2009
Application Number:
20090114951
A memory device can be implemented including word lines connected to an array of memory transistors. Each memory transistor is also connected to bit lines and a select transistor. The select transistors each have their sources connected to a conductive source line, by a shunt and the gate of each select transistor is connected to a select line.
NON-VOLATILE MEMORY ARRAY ARCHITECTURE WITH JOINED WORD LINES
Granted: April 30, 2009
Application Number:
20090109754
In an embodiment, a non-volatile memory array wherein narrow word lines, as small as the minimum feature size width F, in separate strings, are extended outwardly from a non-volatile memory array and joined by wider connector segments. The joined word lines provide new opportunities. First, metal straps that can be formed to overlie the word lines can be joined by metal connector segments to the word lines. The connector segments can serve as an interface between the polysilicon word…
DIFFERENTIAL AMPLIFIER WITH SINGLE ENDED OUTPUT
Granted: April 16, 2009
Application Number:
20090096532
Various embodiments for converting a differential signal to a single ended signal are disclosed. The embodiments comprise a transistor pair for receiving a differential signal; and a tank circuit coupled to the transistor pair. The tank circuit includes a first inductor and one or more capacitors. The embodiments also include a second inductor magnetically coupled to the first inductor to form a balanced/unbalanced inductor (BIMI) arrangement. The BIMI arrangement directly converts the…
APPARATUS AND METHOD FOR PREVENTING SNAP BACK IN INTEGRATED CIRCUITS
Granted: April 16, 2009
Application Number:
20090096501
A method for preventing snap-back in a circuit including at least one MOS transistor having a parasitic bipolar transistor associated with it includes coupling a circuit node including at least one source/drain node of the at least one MOS transistor to a bias-voltage circuit and enabling the bias-voltage circuit to supply a potential to the at least one source/drain node of the at least on MOS transistor, the potential having a magnitude selected to prevent the parasitic bipolar…
COLUMN REDUNDANCY RAM FOR DYNAMIC BIT REPLACEMENT IN FLASH MEMORY
Granted: April 2, 2009
Application Number:
20090086541
A column redundancy system for a non-volatile memory includes a separate companion controller chip that includes a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells. Column redundancy match logic provides a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell, the collection of said addresses stored in the column redundancy RAM…
Charge Pump
Granted: March 19, 2009
Application Number:
20090072889
An improved charge pump design useful in low power applications derives an alternative voltage from a supply voltage. The design can be constructed using PMOS manufactured according to standard processes such that triple well manufacturing processes are not required. The design can incorporate control gate circuitry to increase efficiency and decrease degradation due to the threshold voltage of the transistors used.
METHOD AND APPARATUS FOR CAPTURING IMAGES
Granted: March 19, 2009
Application Number:
20090073283
In a production system including a plurality of imaging devices associated with a respective production tool, an image capture unit, a controller, and an image storage unit, an image capturing method and apparatus is disclosed. The imaging device records the image and transmits the image to the image capture unit. The image capture unit processes the received image and stores the processed image in the image storage unit.
Sense Amplifier
Granted: March 19, 2009
Application Number:
20090073781
A single ended sense amplifier circuit is disclosed that is operable to measure a state of a memory cell. The amplifier can track and compensate for variations in cell current via feedback to maintain precision. The amplifier can be used with low supply voltages while still providing high-speed operation.
CIRCUITS TO DELAY A SIGNAL FROM A MEMORY DEVICE
Granted: March 19, 2009
Application Number:
20090077409
A circuit for delaying an input control signal, comprises a clock circuit to generate a clock signal having a frequency different from an input clock signal to delay and including a clock signal input, a derivative clock signal output, an input to program a frequency ratio between its input clock frequency and its output clock frequency. A clock capturing circuit provides a determined number of delay elements required to provide a delay of an amount of the period of the signal provided…
BIOMETRIC DATA PROCESSING
Granted: March 12, 2009
Application Number:
20090067679
Sets of biometric data related to different types of physical stimuli, e.g., a scanning of a fingerprint and a swiping of a fingerprint, can be compared and a transfer function can be generated based on the comparison.
Variable Resolution Biometric Sensor
Granted: March 12, 2009
Application Number:
20090067684
A variable resolution biometric sensing device includes a sensor manufacture for sensing a biometric stimulus. The sensor device is configured to output data having a resolution selected from among at least two selectable output resolutions.
Fingerprint Sensor with Bump Packaging
Granted: March 12, 2009
Application Number:
20090067690
A biometric sensing device includes a sensor manufacture for sensing a biometric stimulus. The sensor manufacture includes a transitional segment between a side wall and an upper plateau. The transitional segment reduces deformation of a swiped finger, providing a tolerance in the positioning of the sensor device relative to a swiping platform.
AUTO-TRIM CIRCUIT
Granted: March 5, 2009
Application Number:
20090058459
An auto-trim circuit that sets trim bits for an integrated circuit includes a coarse bit calibration circuit for determining a first portion of the trim bits as a set of coarse bits, and a fine bit calibration circuit for determining a second portion of the trim bits as a set of fine bits wherein said fine bits.
