METHOD AND SYSTEM FOR MINIMIZING THE ACCUMULATED OFFSET ERROR FOR AN ANALOG TO DIGITAL CONVERTER
Granted: March 5, 2009
Application Number:
20090058697
A method and system utilized with an analog to digital converter is disclosed. The method and system comprise providing a first conversion on an input signal. In the first conversion, an offset error is added to the input signal to provide a first result. The method and system further includes providing a second conversion on the input signal. In the second conversion, an offset error is subtracted from the input signal to provide a second result. The first and second results are then…
Sensor Security
Granted: March 5, 2009
Application Number:
20090060296
The disclosure herein relates to biometric sensor device security. The biometric integrity of a stimulus; e.g., a finger, that is applied to a biometric sensor can be verified by the biometric sensor. Biometric data related to the stimulus can then be received from the biometric sensor. In order to be more resistant to spoofing techniques, the biometric sensor can monitor for an application continuity of the stimulus during the verifying and receiving steps.
Biometric Control Device
Granted: March 5, 2009
Application Number:
20090058595
Systems and methods for a biometric control device. Actuation of a control device can include direction information which can be used to generate a control signal associated with the actuation. Control signals can facilitate user functions on a recipient device.
NOVEL ROW REDUNDANCY SCHEME IN A MULTICHIP INTEGRATED MEMORY
Granted: February 12, 2009
Application Number:
20090040825
Column redundancy is provided outside of a FLASH memory chip using a separate companion controller chip. The companion chip initially receives and stores fuse address information from the FLASH memory chip for defective memory cells in the FLASH memory. In a read mode of operation, the companion control chip detects receipt of a defective address from the FLASH memory and stores in a redundant shift register redundant data that is downloaded from the FLASH memory chip. The redundant data…
Elliptic Curve Point Transformations
Granted: February 12, 2009
Application Number:
20090041229
In an elliptic curve cryptographic system, point coordinates in a first coordinate system are transformed into a second coordinate system. The transformed coordinates are processed by field operations, which have been modified for operating on the transformed point coordinates. In some implementations, the point coordinates are transformed using a linear transformation matrix having coefficients. The coefficients can be fixed, variable or random. In some implementations, the…
METHOD AND SYSTEM FOR LARGE NUMBER MULTIPLICATION
Granted: February 12, 2009
Application Number:
20090043836
Methods, apparatus and systems for large number multiplication. A multiplication circuit is provided to compute the product of two operands (A and B), at least one of which is wider than a width associated with the multiplication circuit. Each of the operands includes contiguous ordered word-wide operand segments (Aj and Bi) characterized by specific weights j (integer from 0 to k) and i (integer from 0 to m). The multiplication circuit executes a matrix of word-wide operand segment pair…
Masking and Additive Decomposition Techniques for Cryptographic Field Operations
Granted: January 15, 2009
Application Number:
20090016523
Masking and additive decomposition techniques are used to mask secret material used in field operations (e.g., point multiplication operations) performed by cryptographic processes (e.g., elliptic curve cryptographic processes). The masking and additive decomposition techniques help thwart “side-channel” attacks (e.g., power and electromagnetic analysis attacks).
DUAL BUS MATRIX ARCHITECTURE FOR MICRO-CONTROLLERS
Granted: January 15, 2009
Application Number:
20090019207
A dual bus matrix architecture comprising: a first interconnect matrix connected to a plurality of high performance peripherals and having a plurality of master ports and a plurality of slave ports; a second interconnect matrix connected to a plurality of limited bandwidth peripherals and having a plurality of master ports and a plurality of slave ports; and a shared multiport controller connected to one (or more) of the slave ports of the first interconnect matrix and to one (or more)…
Person Recognition Securement Method and Device
Granted: January 8, 2009
Application Number:
20090008459
The invention relates to person authentication systems. The invention proposes incorporating on a chip card intended to be used in a conventional card reader a sensor for spectral information relating to the skin of the person holding the chip card between his thumb and index finger. Spectral recognition uses light-emitting diodes and photodiodes mounted on a flexible substrate comprising interconnecting tracks between the light-emitting diodes and photodiodes on the one hand, and a…
VOLTAGE REGULATOR FOR AN INTEGRATED CIRCUIT
Granted: December 25, 2008
Application Number:
20080315848
A voltage regulator is disclosed. The voltage regulator includes a comparator for providing a gated output signal; and a state machine for receiving the gated output signal. The voltage regulator further includes at least one switch cell controlled by the state machine, for delivering charge to a load. Accordingly, a voltage regulator in accordance with the present invention yields N times (where N is an integer greater than one) the linear efficiency over typical linear regulators…
Method Of Manufacturing A Fingerprint Sensor And Corresponding Sensor
Granted: December 18, 2008
Application Number:
20080309459
The present disclosure relates to a fingerprint sensor device. The device comprises a sensor having a sensitive active region that is electrically connected to a substrate. The device further includes a first resin bump positioned proximate to the sensitive active region. The first resin bump forms a finger guide that positions the finger over the sensitive active region when the finger slides in contact with the first resin bump.
Accurate Transistor Modeling
Granted: December 18, 2008
Application Number:
20080313582
A method and system for generating transistor models. In one embodiment, the method includes generating a transistor model that characterizes a topology of a circuit, and characterizes at least one coupling or at least one interaction between at least two transistors of the circuit.
TRANSPONDER, VERFAHREN ZUM BETRIEB EINES TRANSPONDERS
Granted: December 18, 2008
Application Number:
20080311861
A transponder and method for operating a transponder, which has a capacitor (Cbuf) for storing power transmitted via an air interface and an arithmetic logic unit (10) that can be supplied with the stored power, in which a capacitor voltage (VC) of the capacitor (Cbuf) is compared with a first threshold (V1), in which the capacitor voltage (VC) is compared with a second threshold (V2), whereby the first threshold (V1) and the second threshold (2) are different, in which in a first…
THRESHOLD VOLTAGE METHOD AND APPARATUS FOR ESD PROTECTION
Granted: December 11, 2008
Application Number:
20080304191
An electrostatic discharge protection circuit comprises a comparator coupled between a power supply terminal and ground. The comparator responds to an electrostatic discharge event producing a trigger signal at a comparator output. The comparator comprises a first and second current mirror. The first and second current mirrors each comprise a sense device and a mirror device. The mirror devices are coupled in series between the power supply terminal and ground. The first mirror device…
DEVICE AND METHOD OF SUPPLYING POWER TO TARGETS ON SINGLE-WIRE INTERFACE
Granted: December 4, 2008
Application Number:
20080298385
A single-wire interface communication system is capable of providing both electrical communication of signals and power between devices coupled to the system. Coupled to the single-wire interface is at least one target device which contains a PMOS transistor, a charge storage device, an inverter controlling the PMOS transistor, and a target device function. The charge storage device provides power to the target device function and to the inverter. The PMOS transistor receives power from…
Secure Communications
Granted: December 4, 2008
Application Number:
20080301433
The subject matter of this specification can be embodied in, among other things, an apparatus that includes a verification module to provide information used to identify a user of the apparatus, a memory for storing information used for securing communications transmitted to a remote device, a processing unit for generating a secured communication based on the stored information, and an interface to communicate with a peripheral interface of a host device. The host device configured to…
DMOS DEVICE WITH SEALED CHANNEL PROCESSING
Granted: November 27, 2008
Application Number:
20080290426
A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant…
Frequency Monitor
Granted: November 27, 2008
Application Number:
20080290904
A method and system for monitoring a frequency of a clock signal is disclosed. The method and system comprise dividing a clock signal into a plurality of clock signal components. The method and system further comprise adding a delay to each of the clock signal components and comparing the plurality of signal components with each of the delayed clock signal components to monitor whether the clock signal is within a predetermined frequency range. The method and system includes providing an…
LOW VOLTAGE CHARGE PUMP
Granted: November 27, 2008
Application Number:
20080290930
A single pump stage of a multi-stage charge pump couples a first low-voltage NMOS transistor in series with a first low-voltage PMOS transistor between charge transfer capacitors. A second low-voltage NMOS transistor is coupled between the gate and the source of the first NMOS transistor. A second low-voltage PMOS transistor is coupled between the gate and the source of the first PMOS transistor. Respective boost voltages are applied to gates of the first NMOS transistor and the second…
LOW COST AND LOW VARIATION OSCILLATOR
Granted: November 27, 2008
Application Number:
20080290955
An oscillator circuit for use in integrated circuits. The oscillator circuit includes a delay generation circuit having a current mirror with at least a first current mirror branch and a second current mirror branch, a current source coupled to the first current mirror branch, a capacitive element coupled to the first current mirror branch; and a resistive element coupled to the second current mirror branch. The oscillator circuit further includes a plurality of inverting elements…
