SIGNAL PROCESSING DEVICE AND SIGNAL PROCESSING METHOD
Granted: November 27, 2008
Application Number:
20080293369
A signal processing device and signal processing method is provided that includes a detection unit for detecting a signal strength of a signal, whereby the detection unit is configured to output a detection value that represents the signal strength of the signal; a settable digital filter connected upstream of the detection unit, whereby filter coefficients for setting a transfer characteristic of the filter are assigned to an amplification or attenuation of the signal by the filter; a…
Charge Detector
Granted: November 20, 2008
Application Number:
20080284383
The subject matter of this specification can be embodied in, among other things, an apparatus that includes a battery system, which includes at least one cell and a charge enable device to couple the at least one cell to a charging voltage. The apparatus also includes an excessive voltage detector to output a signal to control the charge enable device. The signal prevents charging of the at least one cell if an excessive charging voltage is detected based on an activation of a clamping…
HIGH DENSITY NON-VOLATILE MEMORY ARRAY
Granted: November 20, 2008
Application Number:
20080285326
A high-density non-volatile memory array. In one aspect of the invention, a memory array circuit includes a plurality of word lines, a plurality of bit-lines, and a plurality of memory cell transistors. The gate of each memory cell transistor is connected to one of the word lines, and the drains and sources of each memory cell transistor are connected only to the bit-lines.
METHOD FOR FABRICATING A BODY TO SUBSTRATE CONTACT OR TOPSIDE SUBSTRATE CONTACT IN SILICON-ON-INSULATOR DEVICES
Granted: November 20, 2008
Application Number:
20080286967
A method of forming an electrical contact between an active semiconductor device layer and a base substrate. The method includes forming a first masking layer over an uppermost surface of the active semiconductor layer, patterning a window in the masking layer, and etching an opening down to the base substrate within an area defined by the window. The opening is filled with a semiconductor contact material while simultaneously adding a dopant to the semiconductor contact material thereby…
CORRELATION DEVICE
Granted: November 20, 2008
Application Number:
20080288570
A correlation device is provided that includes an adder for adding an input signal sequence and an auxiliary signal sequence to obtain an addition signal sequence, and a delay element for delaying the addition signal sequence to obtain the auxiliary signal sequence, whereby the delay element has a plurality of coefficient outputs for providing addition signal sequence coefficients. The correlation device comprises further a linking element for the coefficient-wise linking of an addition…
Managing Power and Timing in a Smart Card Device
Granted: November 13, 2008
Application Number:
20080277482
In some implementations, a mobile device includes a first interface configured to communicably couple to a removable integrated circuit card; a second interface configured to wirelessly communicate with a contactless reader that is external to the mobile device; a communication interface that couples the first interface and the second interface and that is configured to obtain information from an integrated circuit card that is coupled to the first interface in response to receipt by the…
BI-DIRECTIONAL SINGLE WIRE INTERFACE
Granted: November 13, 2008
Application Number:
20080279320
A single-wire, bi-directional communication protocol is provided in which the sending device transmits its clock frequency and its bit transmission period and data through a predefined waveform pattern or “learning sequence” that is recognizable by the receiving device and in a period of time, as measured in number of sending clock cycles, that is known to the receiving device. By clocking the full length of the predefined waveform pattern using its own internal clock, the receiving…
OPTIMAL CONCENTRATION OF PLATINUM IN A NICKEL FILM TO FORM AND STABILIZE NICKEL MONOSILICIDE IN A MICROELECTRONIC DEVICE
Granted: November 13, 2008
Application Number:
20080280439
A method of forming a nickel monosilicide layer on silicon-containing features of an electronic device that includes depositing a nickel film over the silicon-containing features. The nickel film is co-deposited with a selected material. The selected material has an atomic percentage in a range of about 10% to 25%. A single anneal step is then applied to the nickel film thus directly forming the nickel monosilicide layer.
Configurable Memory Protection
Granted: November 6, 2008
Application Number:
20080276051
A method can include receiving a signal associated with an attempted access to data that is stored at a specific location in memory; obtaining a selection value that selects which memory protection register of multiple alternative memory protection registers is to provide a memory protection attribute for the specific location in memory; obtaining, from the selected memory protection register, a memory protection attribute; and controlling access to the specific location in memory based…
Wear Leveling
Granted: November 6, 2008
Application Number:
20080276035
A reference memory location can be designated in a memory device. A memory location can be designated in response to storing data in the memory device. If the identified memory location is associated with the reference memory location then an allocated memory location can be designated relative to the reference memory location, and the allocated memory location can be leveled.
ACCURATE MOTOR SPEED CONTROL
Granted: November 6, 2008
Application Number:
20080272720
A method of and system for controlling a brushless direct current (BLDC) motor includes providing with a lookup table a predetermined corresponding desired revolution time (DRT) for the BLDC motor for an ambient temperature. A Hall device is used to measure an actual revolution time (RT) of the BLDC motor. DRT and RT are compared to change duration of a pulse width modulation (PWM) signal in response to the comparison result. The PWM signal is applied to one of two BLDC motor windings.
DUAL REFERENCE PHASE TRACKING PHASE-LOCKED LOOP
Granted: October 30, 2008
Application Number:
20080266001
A phase-locked loop circuit having a dual-reference input and a phase detector. The dual-reference input is configured to accept both a rising edge of an input clock having a first phase and a falling edge of the input clock having a second phase. The phase detector is coupled to the dual-reference input and is configured to produce a center phase signal based upon and centered in phase between the first and second phases. The phase detector is further configured with a feedback loop to…
DISPLAY CONTROLLER OPERATING MODE USING MULTIPLE DATA BUFFERS
Granted: October 30, 2008
Application Number:
20080266301
A display controller unit for controlling a display on a display panel comprises a first set of registers to hold data to be displayed and a second set of registers loadable from the first set of registers. A set of multiplexers has first data inputs coupled to the first set of registers, second data inputs coupled to the second set of registers, and select inputs. Logic circuitry is coupled to the output of the set of multiplexers and to the control inputs of the multiplexers, the…
CHANNEL DISCHARGING AFTER ERASING FLASH MEMORY DEVICES
Granted: October 30, 2008
Application Number:
20080266982
A post-erase channel clearing procedure for double well, floating gate, non-volatile memory cells. The channel is cleared of charged particles coming from the floating gate after an erase operation in two steps. In the first step the charged particles are pushed into an upper substrate well below the floating gate but not allowed into a deeper well of opposite conductivity type relative to the upper well. After a brief time, T, the charged particles are pushed by a bias voltage into the…
SERIALIZATION OF DATA FOR MULTI-CHIP BUS IMPLEMENTATION
Granted: October 30, 2008
Application Number:
20080270650
Bus communication for components of a system on a chip. In one aspect of the invention, a system includes a matrix operative to select destinations for information on buses connected to the matrix. A first serializer provided on a first device serializes information received from the matrix and sends the serialized information over a communication bus. A second serializer provided on a second device receives the serialized information and deserializes the serialized information, where…
SERIALIZATION OF DATA FOR COMMUNICATION WITH SLAVE IN MULTI-CHIP BUS IMPLEMENTATION
Granted: October 30, 2008
Application Number:
20080270655
Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a slave in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from a bus matrix to the shift registers for serialization and communication to the slave, where the mechanism provides…
SERIALIZATION OF DATA FOR COMMUNICATION WITH DIFFERENT-PROTOCOL SLAVE IN MULTI-CHIP BUS IMPLEMENTATION
Granted: October 30, 2008
Application Number:
20080270656
Bus communication for components of a system on a chip. In one aspect of the invention, a system including bus communication to a slave includes a bridge operative to interface a first bus protocol to a bus matrix that uses a second bus protocol. A first serializer coupled to the bridge serializes information received from the bridge and sends the serialized information over a communication bus. A second serializer coupled to the communication bus receives the serialized information and…
SERIALIZATION OF DATA FOR COMMUNICATION WITH MASTER IN MULTI-CHIP BUS IMPLEMENTATION
Granted: October 30, 2008
Application Number:
20080270667
Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a master in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from the master to the shift registers for serialization, where the mechanism provides deserialized information…
FAST READ PORT FOR REGISTER FILE
Granted: October 23, 2008
Application Number:
20080259712
Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations. A pair of pull-down transistor stacks connected to memory cell latch loops allows a single selected pull-down stack of the pair to toggle a memory cell latch loop to a desired…
METHOD AND APPARATUS FOR GENERATING SYNCHRONOUS CLOCK SIGNALS FROM A COMMON CLOCK SIGNAL
Granted: October 16, 2008
Application Number:
20080252339
A method and system for generating multiple clock signals from a reference clock signal are provided. In one implementation, the system includes a reference clock to generate a reference clock signal having a first frequency, a first prescaler to receive the reference clock signal and generate a first output clock signal having a pre-determined frequency relative to the first frequency of the reference clock signal, and a second prescaler to receive the first output clock signal and…
