CLOCK CIRCUITRY FOR DDR-SDRAM MEMORY CONTROLLER
Granted: July 31, 2008
Application Number:
20080181046
A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and…
CLOCK CIRCUITRY ARCHITECTURE TO IMPROVE ELECTRO-MAGNETIC COMPATIBILITY AND OPTIMIZE PEAK OF CURRENTS IN MICRO-CONTROLLER
Granted: July 31, 2008
Application Number:
20080183924
A system comprises a central processing unit and a set of peripheral units accessible by the CPU and being able to be driven by the same clock source. At least one programmable delay line is located in the clock branch of one of the peripheral units and has a delay selection input that is accessible by software running on the system.
ARCHITECTURE TO CONNECT CIRCUITRY BETWEEN CUSTOMIZABLE AND PREDEFINED LOGIC AREAS
Granted: July 31, 2008
Application Number:
20080183938
An integrated circuit comprises a predefined logic area including a microprocessor coupled to a plurality of peripheral devices including an external bus interface over a system bus. A customizable logic area is accessible by the microprocessor over the system bus. A first I/O bus sends data to an external device. A second I/O bus receives data from an external device. A first set of multiplexers in the predefined logic area have first inputs coupled to an output of the external bus…
UNITY GAIN VOLTAGE BUFFER WITH DUAL SUPPLY VOLTAGE FOR MANAGING CURRENT CONSUMPTION IN LOW VOLTAGE APPLICATIONS
Granted: July 31, 2008
Application Number:
20080179954
A circuit and method for producing an output voltage that replicates an input voltage. A circuit comprises an amplifier stage configured to amplify a difference between an input voltage and a feedback voltage. An output stage is configured to produce an output voltage equal to the input voltage. The output stage configured to be driven by the difference between the input voltage and the feedback voltage. The output stage further comprises a main supply current path configured to provide…
REDUCED ELECTRIC FIELD DMOS USING SELF-ALIGNED TRENCH ISOLATION
Granted: July 24, 2008
Application Number:
20080173940
A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding…
DIFFERENTIAL AMPLITUDE CONTROLLED SAWTOOTH GENERATOR
Granted: July 24, 2008
Application Number:
20080174346
A dual differential sawtooth signal generator includes a first sawtooth voltage generator that has a first capacitor and a second capacitor that are alternately charged with a feedback control source current from a low voltage reference voltage level. A second sawtooth voltage generator has a first discharge capacitor and a second discharge capacitor that are alternately discharged with a feedback control sink current from a high voltage reference voltage level. The output signals of the…
LOW VOLTAGE NON-VOLATILE MEMORY CELL WITH SHARED INJECTOR FOR FLOATING GATE
Granted: July 17, 2008
Application Number:
20080169500
A non-volatile transistor memory array having memory cells, each with a control transistor and a floating gate memory transistor. The cells are arranged in symmetric quadrants with active regions appearing as tic-tac-toe style strips having a central shared drain erase region. Within the drain erase region is an avalanche diode that has overlying regions of four floating gates of the memory transistors and serving to supply erase current of holes and electrons to addressed floating…
EEPROM MEMORY CELL WITH CONTROLLED GEOMETRICAL FEATURES
Granted: July 17, 2008
Application Number:
20080171427
A method of fabricating structures in an electronic device by forming and patterning a first film layer on a substrate into ridges with a photolithographic system. The ridges are formed from an image produced by a first simple geometry photomask where the first photomask has at least one first slot-like feature. The ridges are patterned into the structures which are essentially rectangular in shape and formed from an image produced by a second simple geometry photomask. The second…
BIASING CURRENT TO SPEED UP CURRENT MIRROR SETTLING TIME
Granted: July 10, 2008
Application Number:
20080164948
A current mirror circuit includes a first current-mirror transistor coupled to a second current-mirror transistor. A load is coupled to the second current-mirror transistor. A first current source is coupled to the first current-mirror transistor to cause a bias current to flow through the first current-mirror transistor and a second current source is coupled to the second current-mirror transistor and in parallel with the load to shunt the bias current away from the load.
ERASE VERIFY METHOD FOR NAND-TYPE FLASH MEMORIES
Granted: July 10, 2008
Application Number:
20080165585
An erase-verify method for a NAND flash memory includes a serial double-step erase verify. A verify operation is performed on cells in the unit connected to even word lines by biasing all the even word lines at the read voltage value used in read mode, and by biasing all the odd word lines at the pass voltage value used in read mode of the selected unit. A verify operation is performed on the cells connected to odd word lines by biasing all the odd word lines at the read voltage value…
EEPROM CELL WITH ADJUSTABLE BARRIER IN THE TUNNEL WINDOW REGION
Granted: July 3, 2008
Application Number:
20080157170
An electrically programmable memory cell and corresponding method for fabricating the same, provide a reduced electron tunneling threshold to reduce parasitic substrate currents during cell programming. A floating gate of the cell is formed over an injector dopant region diffused within and encompassed by a first dopant region. Both dopant regions are situated beneath a self-aligned tunneling window of the floating gate. The dopant regions are each high concentration dopants and of…
PHYSICAL ALIGNMENT FEATURES ON INTEGRATED CIRCUIT DEVICES FOR ACCURATE DIE-IN-SUBSTRATE EMBEDDING
Granted: July 3, 2008
Application Number:
20080160670
A method of packaging an integrated circuit die including forming a mask window having a first aperture with a first set of alignment edges and forming an alignment feature on an uppermost surface of the integrated circuit die where the alignment feature has a second set of alignment edges. The alignment feature is inserted into the first aperture. The integrated circuit die is mechanically biased until the first and second set of alignment edges are in physical contact with one another…
COMMUNICATION PROTOCOL METHOD AND APPARATUS FOR A SINGLE WIRE DEVICE
Granted: July 3, 2008
Application Number:
20080159432
The present invention is a noise tolerant communication protocol device and method where a clock signal input triggers ail internal delay clock in an integrated circuit. Data is presented to an input pin and sampled prior to the next external clock pulse based on the internal delay clock. A data pulse value is distinguished by input signal voltage level and not by pulse length. Sampling of data bits is deferred until a signal level is most likely stable, thereby avoiding sampling during…
CHARGE PUMP REGULATOR WITH MULTIPLE CONTROL OPTIONS
Granted: July 3, 2008
Application Number:
20080157729
A voltage generator has a control circuit for controlling a dual-mode charge pump that has multiple control options provided by an optional pull down control signal and an optional stop control signal. The dual-mode charge pump is enabled by a high voltage enable control signal from a control circuit to provide a thigh-voltage output voltage level Vpp or a low-voltage output voltage level Vdd. A current sink transistor is coupled from the output of the dual-mode charge pump to a ground…
METHOD TO REDUCE POWER IN ACTIVE SHIELD CIRCUITS THAT USE COMPLEMENTARY TRACES
Granted: June 26, 2008
Application Number:
20080150574
The present invention provides a method and apparatus for securing an integrated circuit. A pair of conductive security traces are arranged on an integrated circuit. Driver means provide complementary HIGH and LOW voltage levels to a respective first end of each of the conductive security traces. A first switch means temporarily interrupts the driver means and isolates the pair of conductive security traces. A second switch means temporarily connects the first ends of the isolated pair…
KEY PROTECTION MECHANISM
Granted: June 26, 2008
Application Number:
20080152144
A method of protecting secret key integrity in a hardware cryptographic system includes first obtaining an encryption result and corresponding checksum of known data using the secret key, saving those results, then masking the secret key and storing the masked key. When the masked key is to be used in a cryptographic application, the method checks key integrity against fault attacks by decrypting the prior encryption results using the masked key. If upon comparison, the decryption result…
AMPLITUDE CONTROLLED SAWTOOTH GENERATOR
Granted: June 19, 2008
Application Number:
20080143394
A sawtooth voltage generator has a first capacitor that is charged with a variable feedback control current to provide a sawtooth output signal with a controlled amplitude. A feedback loop includes a comparator that compares a version of the sawtooth output signal with a fixed voltage reference to provide a comparator output signal to a phase frequency comparator, the output of which controls a source of the variable feedback control current. A method includes controlling the amplitude…
METHOD AND DEVICE FOR MANAGING A POWER SUPPLY POWER-ON SEQUENCE
Granted: June 19, 2008
Application Number:
20080143395
Apparatus, systems, and methods are disclosed that operate to trigger a reference voltage generator from a supply voltage detector, compare an output voltage level from the reference voltage generator with the a supply voltage, and to generate an enable signal when the supply voltage is greater than the output voltage level. Additional apparatus, systems, and methods are disclosed.
IMPLEMENTATION OF COLUMN REDUNDANCY FOR A FLASH MEMORY WITH A HIGH WRITE PARALLELISM
Granted: June 19, 2008
Application Number:
20080144379
A redundant memory array has r columns of redundant memory cells, r redundant senses, and a redundant column decoder. Redundant address registers store addresses of defective regular memory cells. Redundant latches are provided in n groups of r latches. Redundancy comparison logic compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal to disable the regular senses for one of the n groups…
Supplemental Communication Interface
Granted: June 19, 2008
Application Number:
20080147923
In some implementations, an apparatus includes a first interface having a communication channel through which data is transmitted to or received from a target device and a first control register that is configured to control, based at least in part on its contents, transmission or reception of data through the communication channel; a second interface having a second control register that is configured to control, based at least in part on its contents, transmission or reception of data…
