CHARGE PUMP FOR GENERATION OF MULTIPLE OUTPUT-VOLTAGE LEVELS
Granted: June 12, 2008
Application Number:
20080136500
A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven from the output of a last charge pump stage of the first group and an output coupled to a first voltage node. A second group of cascaded charge-pump stages is provided, the input of the first charge pump stage…
Common Mode Management Between A Current-Steering DAC and Transconductance Filter in a Transmission System
Granted: June 12, 2008
Application Number:
20080136695
Common mode management between a DAC, such as a current-steering DAC, and a transconductance filter in a high-frequency transmission system. In one aspect of the invention, a transmission circuit includes a DAC that provides an analog signal from an input digital signal, and a filter such as a transconductance filter connected to the DAC, the filter receiving the analog signal and filtering the analog signal for transmission. A common mode management circuit connected to the DAC and the…
TEST MODE MULTI-BYTE PROGRAMMING WITH INTERNAL VERIFY AND POLLING FUNCTION
Granted: June 12, 2008
Application Number:
20080141082
A method, device, and processor-readable medium for testing semiconductor devices. A method for testing a semiconductor device comprises: a) entering a multi-byte programming mode; b) programming a plurality of bytes, each byte programmed with identical data; and c) verifying each programmed byte one byte at a time, returning to step b) if any byte fails to verify, otherwise waiting for a next command. A semiconductor device comprises a memory array and a peripheral circuit, the…
REDUCED ELECTRIC FIELD DMOS USING SELF-ALIGNED TRENCH ISOLATION
Granted: June 12, 2008
Application Number:
20080135933
A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding…
SELF-ALIGNED NANOMETER-LEVEL TRANSISTOR DEFINED WITHOUT LITHOGRAPHY
Granted: June 5, 2008
Application Number:
20080128815
A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from silicon-on-insulator (SOI) wafers in a highly uniform and reproducible manner. The method facilitates formation of FinFET devices with improved and reproducible fin height control while providing isolation between source and drain regions of the FinFET device.
BITLINE SELECTION CIRCUITRY FOR NONVOLATILE MEMORIES
Granted: June 5, 2008
Application Number:
20080130365
Bit lines of a memory device are arranged by an interleaving of even and odd bit lines and segregated into an even and odd bank. A discharge network discharges the banks alternately. A bit line selection network alternately connects the banks to a sense amplifier. The bank of odd bit lines is discharged just prior to a selection of the bank of even bit lines for reading and vice-versa. Interleaving even and odd bit lines in combination with alternating selection and discharge of banks…
HIGHLY PARALLEL PIPELINED HARDWARE ARCHITECTURE FOR INTEGER AND SUB-PIXEL MOTION ESTIMATION
Granted: June 5, 2008
Application Number:
20080130748
Disclosed is a pipelined motion estimation system and method. The pipelined motion estimation system includes a current frame input storage means for storing contents of a current frame and a previous frame input storage means for storing contents of one or more previous frames. A sum-of-absolute differences calculation module concurrently determines a best fit motion vector from a plurality of potential motion vectors where each of the plurality of potential motion vectors is based upon…
DEVICE AND METHOD FOR ACCESS TIME REDUCTION BY SPECULATIVELY DECODING NON-MEMORY READ COMMANDS ON A SERIAL INTERFACE
Granted: June 5, 2008
Application Number:
20080133779
An apparatus and method of speculatively decoding non-memory read commands. A command register and decoder, within the apparatus, compares high-order command bits provided on a serial bus with corresponding bits of recognized non-memory read commands. An early non-memory read command is asserted when incoming command bits match a non-memory read command. Early responsive data is prepared speculatively during the time the remainder of command bits is received and decoded. A determination…
CIRCUITS TO DELAY A SIGNAL FROM DDR-SDRAM MEMORY DEVICE INCLUDING AN AUTOMATIC PHASE ERROR CORRECTION
Granted: May 29, 2008
Application Number:
20080123445
A method for delaying a control signal, includes receiving a clock signal, determining a number of delay elements required to generate a first delay equal to a target amount of the period of the clock signal, receiving a data signal having an edge generated at the same time as an edge of the control signal, determining a fraction number equal to the number of delay elements needed to generate a second delay for the data signal or the control signal to align their edges, divided by the…
LOW VOLTAGE COLUMN DECODER SHARING A MEMORY ARRAY P-WELL
Granted: May 29, 2008
Application Number:
20080123415
A plurality of memory sub-arrays are formed in a p-well region. Each of the memory sub-arrays has at least one first-level column decoder that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder is formed outside of the p-well region and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers. During a memory erase mode of operation, a high voltage is provided to bias…
MULTI-COMPONENT ELECTRONIC PACKAGE WITH PLANARIZED EMBEDDED-COMPONENTS SUBSTRATE
Granted: May 29, 2008
Application Number:
20080123318
An electronic multi-component package is assembled by placing multiple electronic components within multiple openings of a package substrate, then depositing and curing adhesive filler in gaps between the components and the inner peripheries of the openings. Circuit features, including conductive interconnects, are formed by thin-film photolithography over both front and back surfaces of the package substrate. Preformed conductive vias through the package substrate provide electrical…
NON-VOLATILE MEMORY TRANSISTOR WITH QUANTUM WELL CHARGE TRAP
Granted: May 22, 2008
Application Number:
20080116447
Quantum well charge trap transistors are disclosed featuring an ion implanted region below a stack of high-low-high bandgap materials arranged in a sandwich structure. Source and drain electrodes on either side of implanted region, as well as a control gate above the stack allow for electrical control. The implanted region, functioning to provide an offset to the threshold for conduction, is less than feature size F using a technique with spacer masks created for implantation, then…
MEMORY ARRAY WITH BIT LINES COUNTERING LEAKAGE
Granted: May 22, 2008
Application Number:
20080117708
Bit lines in a memory array are configured by a select switch matrix to apply the same VD voltage to two adjacent bit lines on the drain side of a selected memory cell for the purpose of blocking charge leakage through the cell adjacent to the selected or addressed cell. The switch matrix features transistors with electrodes connected to bit line segments while control electrodes are connected to control lines from a select decoder. The switch matrix communicates with address decoders…
OPTICAL MEDIA IDENTIFICATIONS
Granted: May 22, 2008
Application Number:
20080117791
Methods, systems, and apparatus, including computer program products for identifying optical disc media. In one aspect a method is provided that includes receiving printed information read from an optical media disc. Identifying a media-type of the optical media disc from the printed information. The printed information can be printed on optical media disc in ink. The printed information can be printed on optical media disc which includes a plurality of stripes. The printed information…
METHOD OF MAKING EEPROM TRANSISTORS
Granted: May 22, 2008
Application Number:
20080119022
A first mask set is used to define parallel active area stripes while a second mask set with memory cell stripes is perpendicular to the first mask set. The second mask set features cell masks with spaced apart branches, one for a non-volatile memory cell. The branch for the non-volatile memory cell has a mask portion for defining a subsurface charge region for communicating charge to a floating gate. The branches can use sub-masks for defining openings that are less than feature size,…
SOLID STATE FIELD EMISSION CHARGE STORAGE
Granted: May 8, 2008
Application Number:
20080105946
Solid state field emission charge storage device is formed by a midgap metal plate and another conductive plate acting as capacitor plates in tunneling relation to a floating charge storage reservoir on a substrate. The plates can be reversibly biased for tunneling of holes or electrons. The devices are tiny islands formed using semiconductor chip fabrication techniques. The islands can form a memory array just as similar islands form a field emitter array for a display screen.
COMPONENT STACKING FOR INTEGRATED CIRCUIT ELECTRONIC PACKAGE
Granted: May 8, 2008
Application Number:
20080105985
Component stacking for increasing packing density in integrated circuit packages. In one aspect of the invention, an integrated circuit package includes a substrate, and a plurality of discrete components connected to the substrate and approximately forming a component layer parallel to and aligned with a surface area of the substrate. An integrated circuit die is positioned adjacent to the component layer such that a face of the die is substantially parallel to the surface area of the…
APPARATUS AND METHOD FOR IMPLEMENTING AN ANALOG-TO-DIGITAL CONVERTER IN PROGRAMMABLE LOGIC DEVICES
Granted: May 8, 2008
Application Number:
20080106452
An apparatus and method for providing an analog-to-digital converter (ADC) in programmable logic devices is disclosed. A plurality of multi-purpose input/output (I/O) blocks is configured to provide analog-to-digital conversion and other I/O functionality. The plurality of multi-purpose I/O blocks is also configured to save power when ADC mode is disabled.
ARRAY SOURCE LINE (AVSS) CONTROLLED HIGH VOLTAGE REGULATION FOR PROGRAMMING FLASH OR EE ARRAY
Granted: May 8, 2008
Application Number:
20080106949
A method for programming a Flash memory array comprises coupling at least one of a current source and a potential source to at least one selected bitline of a Flash memory array, monitoring a potential VAVSS of an array VSS line by means of a comparator, allowing the array VSS line to electrically float until the potential VAVSS is approximately equal to a reference potential Vref, and terminating the programming by de-coupling at least one of the current source and the potential source.
HIGH VOLTAGE VERTICALLY ORIENTED EEPROM DEVICE
Granted: May 8, 2008
Application Number:
20080108212
Apparatus and a method for adding non-volatile memory cells with trench-filled vertical gates to conventional MOSFET surface devices that have their drain and source regions horizontally positioned near the top surface of a substrate. A surface MOSFET device is used as a structural platform to which is added a vertical trench-filled polysilicon gate and a word line region using a small number of additional mask layers and fabrication process modifications. A vertical trench filled…
