GROWTH OF METALLIC NANODOTS USING SPECIFIC PRECURSORS
Granted: May 1, 2008
Application Number:
20080099820
A technique to form metallic nanodots in a two-step process involving: (1) reacting a silicon-containing gas precursor (e.g., silane) to form silicon nuclei over a dielectric film layer; and (2) using a metal precursor to form metal nanodots where the metal nanodots use the silicon nuclei from step (1) as nucleation points. Thus, the original silicon nuclei are a core material for a later metallic encapsulation step. Metallic nanodots have applications in devices such as flash memory…
SYSTEM AND METHOD FOR PROVIDING A NANOSCALE, HIGHLY SELECTIVE, AND THERMALLY RESILIENT BORON ETCH-STOP
Granted: May 1, 2008
Application Number:
20080099840
A method for forming an etch-stop layer and a resulting structure fabricated therefrom. The etch-stop layer has a semiconductor layer having a first surface and a boron layer formed below the first surface of the semiconductor layer. The boron layer has a full-width half-maximum (FWHM) thickness value of less than 100 nanometers. The boron layer is formed by a chemical vapor deposition (CVD) system.
SYSTEM AND METHOD FOR PROVIDING A NANOSCALE, HIGHLY SELECTIVE, AND THERMALLY RESILIENT CARBON ETCH-STOP
Granted: May 1, 2008
Application Number:
20080099882
A method for forming an etch-stop layer and a resulting structure fabricated therefrom. The etch-stop layer is a silicon-germanium layer having a ratio of silicon to germanium of about 50:1 or less, a boron layer formed within the silicon-germanium layer where the boron layer has a full-width half-maximum (FWHM) thickness value of less than 50 nanometers, and a carbon layer formed within the silicon-germanium layer where the carbon layer has an FWHM thickness value of less than 50…
SUCCESSIVE APPROMIXATION ANALOG/DIGITAL CONVERTER AND ASSOCIATED INTEGRATED COMPONENT AND CONVERSION METHOD
Granted: May 1, 2008
Application Number:
20080100490
A successive approximation analog/digital converter is provided, which includes a successive approximation register supplying a digital/analog converter, first means of comparing an input signal of the analog/digital converter to an output signal of the digital/analog converter delivering a first comparison signal, said successive approximation analog/digital converter being synchronised by a clock signal coming from a conversion clock. A method such as this includes dynamic adaptation…
METHOD FOR PREVENTING OVER-ERASING OF UNUSED COLUMN REDUNDANT MEMORY CELLS IN A FLASH MEMORY HAVING SINGLE-TRANSISTOR MEMORY CELLS
Granted: May 1, 2008
Application Number:
20080101118
A method is provided for testing and for preventing over-erasure of unused redundant memory cells that can be subsequently used to replace defective memory cells in a Flash memory. An unused redundant memory cell is preprogrammed and tested simultaneously with each group of n memory cells. The selected unused redundant memory cell is preprogrammed only a couple of times and then skipped for the rest of the preprogramming pulses applied to the regular core cells. Each unused redundant…
PROGRAMMING PULSE GENERATOR
Granted: May 1, 2008
Application Number:
20080101124
A signal generator circuit is configured to generate program signals for a memory array. The program signals are applied to word lines in the memory array, and have a transient state based on a coupling characteristic of the word lines and selector gates. The transient state is configured to minimize coupling between the word lines and the gates of the selectors so that a state of each selector remains unchanged during the transient state.
ADAPTIVE GATE VOLTAGE REGULATION
Granted: May 1, 2008
Application Number:
20080101133
A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of the bit line select voltage to a gate of a transistor receiving the select voltage causes the transistor to conduct, and the application of the bit line select voltage to a gate of a transistor receiving the unselect voltage biases the transistor off.
METHOD FOR PROVIDING A NANOSCALE, HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) ON INSULATOR
Granted: May 1, 2008
Application Number:
20080099754
A method and resulting high electron mobility transistor comprised of a substrate and a relaxed silicon-germanium layer formed over the substrate. A dopant layer is formed within the relaxed silicon-germanium layer. The dopant layer contains carbon and/or boron and has a full-width half-maximum (FWHM) thickness value of less than approximately 70 nanometers. A strained silicon layer is formed over the relaxed silicon-germanium layer and is configured to act as quantum well device.
OUTPUT INTERFACING DEVICE COMPENSATED IN LOAD AND CORRESPONDING ELECTRONIC CIRCUIT
Granted: April 24, 2008
Application Number:
20080094118
An output interfacing device is provided, which receives at its input an input signal and provides at its output, an output signal to an external load. The output interfacing device invertes the effect of the capacitance of the external load on the slew rate of the output signal.
ADAPTIVE REGULATOR FOR IDLE STATE IN A CHARGE PUMP CIRCUIT OF A MEMORY DEVICE
Granted: April 17, 2008
Application Number:
20080089140
An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.
Read-data stage circuitry for DDR-SDRAM memory controller
Granted: April 17, 2008
Application Number:
20080091903
A circuit for sampling data from a memory device comprises a circuit for providing a clock signal to the memory device, a data bus carrying data at twice the rate of the clock signal, a circuit for providing a control signal to indicate the period of time where data are valid, and a set of registers whose content is triggered by both edges of a signal resulting from the delay of the control signal. The set of registers is divided into several sub-parts, each sub-part loading the value of…
Method for fabricating conducting plates for a high-Q MIM capacitor
Granted: April 17, 2008
Application Number:
20080089007
A method of forming one or more capacitors on or in a substrate and a capacitor structure resulting therefrom is disclosed. The method includes forming a trench in the substrate, lining the trench with a first copper-barrier layer, and substantially filling the trench with a first copper layer. The first copper layer is substantially chemically isolated from the substrate by the first copper-barrier layer. A second copper-barrier layer is formed over the first copper layer and a first…
APPARATUS AND METHOD FOR PROVIDING A TEMPERATURE COMPENSATED REFERENCE CURRENT
Granted: April 10, 2008
Application Number:
20080084240
An apparatus and method for providing a temperature compensated reference current in an electronic device is disclosed. The temperature compensated reference current is compensated for temperature and other circuit variations. The reference current is provided by an improved reference current generator and may be used in a memory device or any other desired circuit.
APPARATUS FOR ELIMINATING LEAKAGE CURRENT OF A LOW Vt DEVICE IN A COLUMN LATCH
Granted: April 10, 2008
Application Number:
20080084767
An improved CMOS high-voltage latch that stores data bits to be written to memory cells of a non-volatile memory is connected to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation. During a high-voltage write mode of operation, the HV terminal is connected to a HIGH-VOLTAGE supply voltage. A cross-coupled high-voltage CMOS latch is connected between the HV terminal and a ground terminal and has a latch input node B and a latch output node A.…
PIPELINED ANALOG-TO-DIGITAL CONVERTER HAVING A POWER OPTIMIZED PROGRAMMABLE DATA RATE
Granted: April 3, 2008
Application Number:
20080079622
The present invention is related to a pipelined analog-to-digital converter (ADC) utilizing a power distribution scheme selectively delivering both constant and variable reference currents in selected proportions to a plurality of stages and operational transconductive amplifiers (OTAs). This permits the ADC to maintain an optimized speed over power consumption ratio over a wide data rate range. Since the invention is capable of supporting a large operating range while maintaining very…
APPARATUS AND METHOD INCORPORATING DISCRETE PASSIVE COMPONENTS IN AN ELECTRONIC PACKAGE
Granted: March 27, 2008
Application Number:
20080075841
An apparatus and method for incorporating discrete passive components into an integrated circuit package. A metal layer is formed over a surface of a substrate. A layer of photosensitive material is then formed over the metal layer. Using standard photolithographic processing, a pattern is formed with the photosensitive material to expose at least one region of the metal layer. The remaining photosensitive material protects the underlying metal during metal etching. The substrate is then…
SONOS MEMORY ARRAY WITH IMPROVED READ DISTURB CHARACTERISTIC
Granted: March 20, 2008
Application Number:
20080068896
A PMOS non-volatile memory array using SONOS transistors having program and erase threshold voltages for representing digital logic states of zero and one and selected to optimize read disturb characteristics. The threshold voltages are linearly convergent and separated by at least 0.5 volts for a charge retention time of at least 10 years, with the threshold voltages defining a window wherein a read voltage for selected memory transistors can be held flat and not intersect the threshold…
METHOD FOR CLEANING A SURFACE OF A SEMICONDUCTOR SUBSTRATE
Granted: March 20, 2008
Application Number:
20080069952
A method of cleaning and oxidizing a substrate, for example, a silicon wafer, and forming a film (e.g., silicon dioxide) in-situ by placing the substrate in a chamber, pumping-down the chamber to a predetermined subatmospheric pressure, and elevating a temperature of the substrate within the chamber. Cleaning begins by releasing hydrogen gas into the chamber for a time period of, for example, 5 seconds to 300 seconds. The hydrogen gas, along with any contaminants, are then evacuated from…
BI-PROCESSOR ARCHITECTURE FOR SECURE SYSTEMS
Granted: March 20, 2008
Application Number:
20080072051
Systems, methods and program products for a first central processing unit (CPU) configured to perform tasks that do not require manipulation of sensitive information and a second CPU that is configured to perform tasks that manipulate the sensitive information on behalf of the first CPU. The first CPU and the second CPU can communicate through a secure interface. The first CPU cannot access the sensitive information within the second CPU.
DIE ATTACH PADDLE FOR MOUNTING INTEGRATED CIRCUIT DIE
Granted: March 13, 2008
Application Number:
20080061416
An electrical package for an integrated circuit die which comprises a die-attach paddle for mounting the integrated circuit die. The die-attach paddle has at least one down-set area located on a periphery of the die-attach paddle. The down-set area has an upper surface and a lower surface, with the upper surface configured to electrically couple a first end of a first electrically conductive lead wire. A second end of the first electrically conductive lead wire is bonded to the…
