DIE ATTACH PADDLE FOR MOUNTING INTEGRATED CIRCUIT DIE
Granted: March 13, 2008
Application Number:
20080064145
An electrical package for an integrated circuit die which comprises a die-attach paddle for mounting the integrated circuit die. The die-attach paddle has at least one down-set area located on a periphery of the die-attach paddle. The down-set area has an upper surface and a lower surface, with the upper surface configured to electrically couple a first end of a first electrically conductive lead wire. A second end of the first electrically conductive lead wire is bonded to the…
A STACKED-DIE ELECTRONICS PACKAGE WITH PLANAR AND THREE-DIMENSIONAL INDUCTOR ELEMENTS
Granted: March 6, 2008
Application Number:
20080054428
An apparatus and a method for producing three-dimensional integrated circuit packages. In one embodiment, an electronics package with at least two dice are stacked one atop another is disclosed. A top die is of smaller size compared with a bottom die such that after a die attach operation, wire-bond pads of the bottom die will be exposed for a subsequent wire bonding operation. The bottom die contains contact pads on the front side that couple with one or more passive components…
MICROCONTROLLER INTERFACE WITH HALL ELEMENT
Granted: March 6, 2008
Application Number:
20080054830
A device controller system incorporates an inexpensive Hall element to detect motion of a brushless DC motor. A magnet, which is part of a motor rotor, passes by the Hall element producing a Hall voltage each rotation. The Hall voltage is coupled through an interface port to a comparator within a process controller. A microprocessor within the process controller calculates a control response based on a comparator output signal. The interface port is rapidly configured to provide signals…
LEAKAGE IMPROVEMENT FOR A HIGH-VOLTAGE LATCH
Granted: March 6, 2008
Application Number:
20080054973
An improved CMOS high-voltage latch stores data bits to be written to memory cells of a non-volatile memory has two cross-coupled CMOS inverters. One of the inverters has a pull-down leg that includes a pass-gate high-voltage NMOS transistor that is connected between a latch output node and a second high-voltage, low-threshold NMOS pull-down transistor that is connected to ground. A gate of the pass-gate high-voltage NMOS transistor receives a standby signal with a logic HIGH value of at…
METHOD AND APPARATUS TO PREVENT HIGH VOLTAGE SUPPLY DEGRADATION FOR HIGH-VOLTAGE LATCHES OF A NON-VOLATILE MEMORY
Granted: March 6, 2008
Application Number:
20080056015
An improved cross-coupled CMOS high-voltage latch that is used for storing data bits to be written to memory cells of a non-volatile memory is provided with a switching circuit that, during writing of data bits into the memory cells of the latch, provides a high series impedance between one leg of the latch and ground to limit leakage current. A large number of latches are connected in parallel and their accumulated leakage currents are limited by the switching circuit to prevent…
METHOD AND APPARATUS TO PREVENT HIGH VOLTAGE SUPPLY DEGRADATION FOR HIGH-VOLTAGE LATCHES OF A NON-VOLATILE MEMORY
Granted: March 6, 2008
Application Number:
20080056020
An improved cross-coupled CMOS high-voltage latch that is used for storing data bits to be written to memory cells of a non-volatile memory is provided with a switching circuit that, during writing of data bits into the memory cells of the latch, provides a high series impedance between one leg of the latch and ground to limit leakage current. A large number of latches are connected in parallel and their accumulated leakage currents are limited by the switching circuit to prevent…
METHOD FOR FABRICATING A THICK COPPER LINE AND COPPER INDUCTOR RESULTING THEREFROM
Granted: March 6, 2008
Application Number:
20080057658
A method of forming one or more inductors on a substrate is disclosed. The method includes forming a first dielectric material over the substrate, forming a trench in the first dielectric material, and substantially filling the trench with copper to form the one or more inductors. The first dielectric material is removed and a second dielectric material is formed over the copper. The second dielectric material is removed from an uppermost portion of the copper, thus leaving a portion of…
STACKABLE PACKAGES FOR THREE-DIMENSIONAL PACKAGING OF SEMICONDUCTOR DICE
Granted: February 28, 2008
Application Number:
20080048308
An apparatus and a method for packaging semiconductor devices. The apparatus includes a substrate strip component of a leadless three-dimensional stackable semiconductor package having mounting contacts on, for example, four peripheral edges. The substrate strip may either be fabricated for mounting a single electrical component (e.g., an integrated circuit die) or a plurality of substrate strips may be laid out in an X-Y matrix pattern which may later be singulated into individual…
METHOD FOR MANAGING TRANSITIONS IN A THREE-PHASE BLDC MOTOR AND CORRESPONDING DEVICE
Granted: February 28, 2008
Application Number:
20080048594
A method is provided for managing at least one transition in a three-phase BLDC motor describing a cycle including six successive states, wherein the motor obtains first, second and third synchronisation signals. The synchronisation signals are respectively associated with first, second and third coils of the motor. The method includes the following steps, for each current transition associated with the switching of the motor from a current state to a next state: selecting a current…
HETROJUNCTION BIPOLAR TRANSISTOR (HBT) WITH PERIODIC MULTILAYER BASE
Granted: February 28, 2008
Application Number:
20080050883
A method and resulting electronic device utilizing a periodic multi-layer (ML) and/or superlattice (SL) structures in the base of a SiGe heterojunction bipolar transistor (HBT) is disclosed. The SL is a special case of an ML, in which layers that are chemically different from adjacent neighbors are successively repeated. The use of the ML in electronic and photonic devices is enables strategic engineering of the energy band gap and carrier mobilities. Principles disclosed herein relate…
METHODS AND COMPOSITIONS FOR WET ETCHING
Granted: February 21, 2008
Application Number:
20080041813
A composition comprising an aqueous solution of: a wet-etch formulation that is proven to etch copper; and a wetting agent. Exemplary wet-etch formulations include a mixture of a strong inorganic acid, such as sulfuric acid or hydrofluoric acid, and an oxidizing agent such as hydrogen peroxide, and further include ammonium persulfate. Exemplary wetting agents include organic acids such as citric acid, acetic acid, oxalic acid, or formic acid. Processes of using the compositions for…
A METHOD TO PROVIDE SUBSTRATE-GROUND COUPLING FOR SEMICONDUCTOR INTEGRATED CIRCUIT DICE CONSTRUCTED FROM SOI AND RELATED MATERIALS IN STACKED-DIE PACKAGES
Granted: February 21, 2008
Application Number:
20080044947
An apparatus and a method for packaging semiconductor devices. Disclosed are multi-die packaging apparatuses and techniques, especially useful for integrated circuit dice involving insulative substrates, such as silicon-on-insulator (SOI), where grounding of a base layer is not reasonably practical. Disclosed is a means for effectively grounding all layers of an integrated circuit device regardless of whether the device makes direct contact with a die-attach paddle.
AUTONOMOUS ANTIFUSE CELL
Granted: February 21, 2008
Application Number:
20080043511
An autonomous antifuse cell providing protection against intruders includes an antifuse, sense circuitry, feedback circuitry, program circuitry, and blocking circuitry. The blocking circuitry blocks access of any programming voltage input signals to the antifuse device if the antifuse is previously blown and when power is applied to the cell. In an exemplary embodiment, the antifuse cell uses only a single external access pin. Once the antifuse device is blown and during subsequent…
HIGH EFFICIENCY BI-DIRECTIONAL CHARGE PUMP CIRCUIT
Granted: February 21, 2008
Application Number:
20080042731
A charge pump circuit having a first voltage node acting as an input when the charge pump circuit boosts negative voltages, and acting as an output when the charge pump circuit boosts positive voltages and a second voltage node acting as an input when the charge pump circuit boosts positive voltages, and acting as an output when the charge pump circuit boosts negative voltages. The charge pump circuit further has a first pump capacitor, a second pump capacitor, a first auxiliary…
EEPROM MEMORY ARRAY HAVING 5F2 CELLS
Granted: February 21, 2008
Application Number:
20080042185
A non-volatile memory array featuring cells with split gate transistors and an overall area extent of 5F2, i.e. five times the minimum lithographic feature size squared. While smaller calls are known, the cells of the present invention each have a select device and a floating gate transistor with adjacent cells having shared source-drain lines, all controlled by only four lines including two bit lines, a word line and a select gate line. The lines are extended beyond the boundary of the…
CONTACTLESS NONVOLATILE MEMORY ARRAY
Granted: February 14, 2008
Application Number:
20080035982
An array of memory cells with non-volatile memory transistors having a compact arrangement of diagonally symmetric floating gates. The floating gates have portions extending in both X and Y directions, allowing them to be charged through a common tunnel oxide 8stripe that runs under a portion of each, for example a portion running in the X-direction while the two Y-direction portions serve to establish a channel. Shared source/drain regions are established between and in proximity to the…
CONFIGURABLE UNIVERSAL INTERCONNECT DEVICE
Granted: February 14, 2008
Application Number:
20080036098
A universal interconnect device for mounting and interconnecting a semiconductor integrated circuit die in preparation for mounting to another substrate such as a printed circuit board. The device consists of a laminate substrate having a first surface upon which the integrated circuit die may be mounted. Underlying and surrounding the die mount area is a plurality of substantially concentric electrically-conductive paths. Each of the plurality of paths is electrically isolated from each…
APPARATUS AND METHOD FOR CHARGE PUMP SLEW RATE CONTROL
Granted: February 14, 2008
Application Number:
20080036516
An apparatus and method for improving memory cell reliability is disclosed. The slew rate is reduced in an applied voltage signal used to program a memory cell when Fowler-Nordheim (FN) tunneling injection is detected. The applied programming signal is provided by a charge pump that is preferably a regulated charge pump. The charge pump is selectively controlled by a slew rate control circuit when FN tunneling injection is detected by a voltage level detection circuit at a predetermined…
HIGH-SPEED, SELF-SYNCHRONIZED CURRENT SENSE AMPLIFIER
Granted: February 14, 2008
Application Number:
20080037345
A sense amplifier circuit and a method for reading a memory cell. A circuit comprises a first bit line associated with a memory cell. A first input of a latch is coupled to the first bit line and a second input of the latch is coupled to a second node. There is a means for biasing the first input and the second input of the latch to a differential voltage between the first node coupled to the first bitline and the second node. There is also a means for switching the latch according to…
EMBEDDED SOFTWARE CAMOUFLAGE AGAINST CODE REVERSE ENGINEERING
Granted: February 14, 2008
Application Number:
20080040593
Methods and apparatus for identifying a first flow control instruction in an executing program, the first instruction being associated with a first program address at which program execution will continue after execution of the first instruction. A determination is made as to whether the first program address is protected. If the first program address is protected, a first alternate program address is substituted for the first program address such that program execution will continue at…
