MEMORY ARCHITECTURE WITH ADVANCED MAIN-BITLINE PARTITIONING CIRCUITRY FOR ENHANCED ERASE/PROGRAM/VERIFY OPERATIONS
Granted: February 7, 2008
Application Number:
20080031075
The present invention provides a solution for long master bit lines in a large capacity memory device. A master bit line is partitioned by at least one switching transistor placed on the master bit line.
CONDUCTIVITY CONTROL OF WATER CONTENT IN SOLVENT STRIP BATHS
Granted: January 31, 2008
Application Number:
20080023045
A system and method for control of water content in a strip bath. The method to control water content in a solvent bath used for cleaning of semiconductor parts in the back end of semiconductor manufacturing requires addition of water to replace evaporated water. This is done by periodically adjusting a conductivity setpoint at least in part based on the elapsed chemical bathlife and at least in part based on the number of semiconductor parts that have been processed in the bath. The…
CAPACITIVE NODE ISOLATION FOR ELECTROSTATIC DISCHARGE CIRCUIT
Granted: January 31, 2008
Application Number:
20080024169
Capacitive node isolation circuitry in an integrated circuit eliminates the creation of hot spots (stored charge) on high capacitive nodes during a test of electrostatic discharge (ESD) protection circuitry of the integrated circuit or during any ESD event occurring while the integrated circuit is in a standby mode. The isolation circuitry includes a standby mode logic circuit responsive to a standby mode signal received at one of its inputs and provides an output signal to a gate of an…
ADAPTIVE NOISE FILTERING FOR REDUCING IMAGER NOISE IN DIGITAL IMAGE APPLICATIONS
Granted: January 31, 2008
Application Number:
20080025630
A noise filtering engine and method that removes fixed and random pattern noise from a digital image source. The engine may be implemented, for example, as a subsystem of a hardware-based pipeline for digital image processing or in software or a combination of hardware and software. The noise reduction engine consists of one or more hardware blocks to facilitate high throughout and high-performance operations. The engine has a significant degree of flexibility and programmability…
NOISE IMMUNE RC TRIGGER FOR ESD PROTECTION
Granted: January 10, 2008
Application Number:
20080007882
An ESD protection circuit incorporates an ESD shunt device triggered by an ESD trigger network. In non-powered situations, a first RC time constant in the ESD trigger network, corresponds with the time range of the onset an ESD event and controls application of the ESD shunt device in response to the ESD event. A second RC time constant in a shunt trigger network is selected to be longer than the first RC time constant and holds-off triggering of a shunt device during ESD shunt…
DATA REGISTER WITH EFFICIENT ERASE, PROGRAM VERIFY, AND DIRECT BIT-LINE MEMORY ACCESS FEATURES
Granted: January 3, 2008
Application Number:
20080005416
A programmable memory device circuit comprising a sense and programming circuit, a latch circuit, a verify circuit for coupling the latch circuit logic value to a shared indicator line, and a direct memory access circuit coupled to the verify circuit. The DMA circuit couples a bit line to the verify circuit, and the verify circuit couples the direct memory access circuit to a shared verify indicator and DMA line.
A METHOD FOR MANIPULATION OF OXYGEN WITHIN SEMICONDUCTOR MATERIALS
Granted: November 15, 2007
Application Number:
20070262295
Methods and electronic devices fabricated by those methods are disclosed where the method allows controlled movement of oxygen during fabrication of electronic and photonic devices, facilitated by a technique of oxygen updiffusion (OUD). The method includes fabrication of a compound semiconductor film, doped with either carbon or boron, over a substrate and incorporating a quantity of oxygen into either the substrate or an adjacent film layer. One or more anneal steps may be used as a…
THREE-DIMENSIONAL PACKAGING SCHEME FOR PACKAGE TYPES UTILIZING A SACRIFICIAL METAL BASE
Granted: November 15, 2007
Application Number:
20070262435
An apparatus and a method for packaging semiconductor devices. The apparatus is applicable to many types of contemporary packaging schemes that utilize a sacrificial metal base strip. Tunnels formed through an encapsulation area surrounding the device and associated bond wires are filled with a metallic conductor by, for example, electroplating, and extend bottom contact pads to an uppermost portion of the encapsulated area. The sacrificial metal base strip serves as a plating bus and is…
METHOD AND MATERIALS TO CONTROL DOPING PROFILE IN INTEGRATED CIRCUIT SUBSTRATE MATERIAL
Granted: November 15, 2007
Application Number:
20070264795
Methods and materials for silicon on insulator wafer production in which the doping concentration in a handle wafer is sufficiently high to inhibit dopant from diffusing from the bond wafer during or after bonding to the handle wafer.
Method and Apparatus to Test the Power-on-Reset Trip Point of an Integrated Circuit
Granted: November 15, 2007
Application Number:
20070266280
Circuitry for testing a power-on-reset circuit in an integrated circuit includes a high-voltage detector coupled to a first I/O pad of the integrated circuit. A power-on-reset circuit in the integrated circuit has an output coupled to a driver circuit that is powered by the high-voltage. A second I/O pad of the integrated circuit is coupled to the output of the driver circuit. The driver circuit may be enabled by a signal provided on a third I/O pad of the integrated circuit.
Low resistance integrated MOS structure
Granted: November 8, 2007
Application Number:
20070257278
The present invention is related to a metal-oxide semiconductor field-effect transistor (MOSFET) having a symmetrical layout such that the resistance between drains and sources is reduced, thereby reducing power dissipation. Drain pads, source pads, and gates are placed on the MOSFET such that the distances between drains, sources, and gates are optimized to reduce resistance and power dissipation. The gates may be arranged in a trapezoidal arrangement in order to maximize a ratio of the…
MEMORY CELL WITH REDUCED SIZE AND STANDBY CURRENT
Granted: November 8, 2007
Application Number:
20070257298
A present invention is a method, and resulting device, for fabricating memory cells with an extremely small area and reduced standby current. The small area is accomplished by a judicious use of spacers which allows a tunnel window of a storage device to be fabricated in close proximity to an associated select gate and with a reduced gate width compared to typical devices. The tunnel window is recessed within an upper surface of a substrate. The tunnel window recess is made possible by…
MULTI-COMPONENT PACKAGE WITH BOTH TOP AND BOTTOM SIDE CONNECTION PADS FOR THREE-DIMENSIONAL PACKAGING
Granted: November 1, 2007
Application Number:
20070252255
An apparatus and a method for packaging semiconductor devices. The apparatus is a three-dimensional electronic package comprising one or more electronic components, a plurality of electrical contact pads, and a plurality of electrically conductive three-dimensional plugs formed through an encapsulant. Specific ones of the plurality of electrical contact pads are electrically coupled to the one or more electronic components on an uppermost surface of the plurality of electrical contact…
METHOD AND CIRCUIT FOR A VOLTAGE SUPPLY FOR REAL TIME CLOCK CIRCUITRY BASED ON VOLTAGE REGULATED CHARGE PUMP
Granted: November 1, 2007
Application Number:
20070252564
A versatile voltage regulator accommodates either an Alkaline or Lithium-Ion battery main battery and provides low-current power for a real time clock module and for charging a backup battery. Depending upon the battery power source that is used, the present invention provides a best circuit configuration for efficient power conversion. If the power converter according to the present invention provides a regulated output voltage that is greater than the main battery voltage of an…
Method of optimising writing by a master block into a fifo type interfacing device between this master block and a slave block, and the corresponding computer program product
Granted: November 1, 2007
Application Number:
20070255911
A method for optimising writing by a master block into an interfacing device between the master block and a slave block. The method includes a step for transformation of a code into assembler language, done before the code in machine language is obtained and including the following steps: transformation of all static unit writes comprising more than one word from the assembler language code into one-word static unit writes; search for each set of N successive static one-word unit writes;…
SERIAL COMMUNICATIONS BUS WITH ACTIVE PULLUP
Granted: October 25, 2007
Application Number:
20070247184
A dual-wire communications bus circuit, compatible with existing two-wire bus protocols, includes a first and second part of the communications bus circuit to couple to a communications bus. The bus has a first line for carrying data signals from a master device to one or more slave devices and a second line to carry a clock signal between the devices A pullup resistor is located in each part of the communications bus circuit; the pullup resistor in the first part couples to the first…
TARGETS FOR ALIGNMENT OF SEMICONDUCTOR MASKS
Granted: October 25, 2007
Application Number:
20070248898
Alignment of mask layers in semiconductor manufacturing is carried out by using alignment lines having at least one row of diffractively reflecting or scattering features on the lines. The features are made using a phase shift mask which, in combination with selected photoresist, suppresses second and higher order lobes, thereby allowing the features to be more closely spaced than by lithography. The features appear as light reflecting or scattering dots or spots in rows on ridges of…
Output buffer receiving first and second input signals and outputting an output signal, and corresponding electronic circuit
Granted: October 25, 2007
Application Number:
20070250554
An output buffer is provided, to which first and second input signals are applied and that delivers an output signal. The output buffer includes a second offset switching stage installed in cascade downstream from a first switching stage. The second offset switching stage generates control points shifted in time with respect to memory points.
HIGH SPEED DUAL-WIRE COMMUNICATIONS DEVICE REQUIRING NO PASSIVE PULLUP COMPONENTS
Granted: October 25, 2007
Application Number:
20070250652
A dual-wire communications bus circuit, compatible with existing two-wire protocols, includes a first and second part of the communications bus circuit to couple to a communications bus. The bus has a first line for carrying data signals from a master device to a slave device and a second line to carry a clock signal between the devices. To improve data throughout and reduce noise, an active pullup device is located in at least one part of the communications bus circuit, the active…
Low-dropout voltage regulator with a voltage slew rate efficient transient response boost circuit
Granted: October 18, 2007
Application Number:
20070241728
A low-dropout (LDO) voltage regulator for generating an output voltage is disclosed. The voltage regulator includes a startup circuit, a curvature corrected bandgap circuit, an error amplifier, a metal oxide semiconductor (MOS) pass device and a voltage slew rate efficient transient response boost circuit. The MOS pass device has a gate node which is coupled to the output of the error amplifier, and a drain node for generating the output voltage. The voltage slew rate efficient transient…
