POWER EFFICIENT STARTUP CIRCUIT FOR ACTIVATING A BANDGAP REFERENCE CIRCUIT
Granted: October 18, 2007
Application Number:
20070241735
A power efficient startup circuit for activating a bandgap reference circuit is disclosed. The startup circuit uses a voltage supply having a voltage level to initiate the flow of a startup current used to activate the bandgap reference circuit. When the bandgap reference circuit starts, the startup circuit slowly charges a capacitor using the voltage supply when the startup current is flowing. The startup circuit disables quiescent current when the bandgap reference circuit is activated…
METHOD OF FORMING A SHALLOW TRENCH ISOLATION STRUCTURE WITH REDUCED LEAKAGE CURRENT IN A SEMICONDUCTOR DEVICE
Granted: October 11, 2007
Application Number:
20070235836
A method for fabricating a shallow trench isolation structure for a subthreshold kink-free semiconductor memory device includes the steps of forming a nitride-oxide-nitride-oxide stack on top of a semiconductor substrate, etching shallow trenches in selected areas and filling them with an insulating material so that it is level with the top nitride layer, removing the top nitride layer, depositing a protective material on top of a first device area, removing the top oxide layer in a…
Secure biometric processing system and method of use
Granted: October 11, 2007
Application Number:
20070237366
A secure biometric processing system is disclosed. The system comprises a processing system for providing image acquisition and biometric comparison. The processing unit utilizes public key cryptography for handling templates securely and authenticating operations using the template. The system includes a complete biometric engine which implements image reconstruction, template extraction and matching. The secure design of the system combines complete privacy with security, while…
APPARATUS AND METHOD FOR THE DETECTION OF AND RECOVERY FROM INAPPROPRIATE BUS ACCESS IN MICROCONTROLLER CIRCUITS
Granted: October 4, 2007
Application Number:
20070233429
An inappropriate-access module is incorporated in a computer system along with other computer system modules. The inappropriate-access module is connected to a read address decoder and controlling logic located within various other modules. The inappropriate-access module detects inappropriate read accesses or the occurrence of the inappropriate access during operations performed on related sensitive system resources in accompanying computer system modules. The inappropriate-access…
Reverse polish notation device for handling tables, and electronic integrated circuit including such a processing device
Granted: September 27, 2007
Application Number:
20070226461
The disclosure relates to a reverse Polish notation processing device making it possible to execute a set of instructions and implementing management of a stack whose size is variable. The device includes a storage device including a random access memory; a device for managing a stack pointer, which is a physical address, in said random access memory, associated with a reference stage of the stack; and a device for managing reference element pointer(s), which is a physical address, in…
Secure biometric processing system and method of use
Granted: September 27, 2007
Application Number:
20070226514
A secure biometric processing system is disclosed. The system comprises a processing system for providing image acquisition and biometric comparison. The processing unit utilizes public key cryptography for handling templates securely and authenticating operations using the template. The system includes a complete biometric engine which implements image reconstruction, template extraction and matching. The secure design of the system combines complete privacy with security, while…
Secure biometric processing system and method of use
Granted: September 27, 2007
Application Number:
20070226515
A secure biometric processing system is disclosed. The system comprises a processing system for providing image acquisition and biometric comparison. The processing unit utilizes public key cryptography for handling templates securely and authenticating operations using the template. The system includes a complete biometric engine which implements image reconstruction, template extraction and matching. The secure design of the system combines complete privacy with security, while…
Electronic driver device for an external load for which the slew rate of the output signal is independent of the external load capacity and the corresponding integrated component
Granted: September 6, 2007
Application Number:
20070205814
This disclosure relates to an electronic driver device for an external load to which an input signal is applied at its input and that produces an output signal to the external load from its output. Such an electronic driver device includes elements that reduce dependence of the slew rate of the output signal on the external load capacitance.
REGISTRATION MARK WITHIN AN OVERLAP OF DOPANT REGIONS
Granted: September 6, 2007
Application Number:
20070207589
A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active…
DETECTOR OF DIFFERENTIAL THRESHOLD VOLTAGE
Granted: August 30, 2007
Application Number:
20070200599
A differential threshold voltage level detection circuit receives a differential voltage pair as an input, applying each component of the differential pair to an individual voltage shifting circuit. Each voltage shifting circuit is configured with a regulated current producing a shifted and a non-shifted version in-phase. For a shifted set of output differential voltages, the shift magnitude is proportional to the current entering a shifting circuit and is configured to be less than a…
Apparatus and method for reducing power consumption in electronic devices
Granted: August 30, 2007
Application Number:
20070200595
An apparatus and method for reducing power consumption in a programmable logic device (PLOD) having multiple logic blocks and macrocells. Power consumption is reduced by detecting programmable switch values in each macrocell and generating a clock control signal based on the switch values. The clock control signal controls a macrocell buffer used for compensating for distortion of clock signals inputted to the macrocell. The macrocell buffer is disabled if the clock signals are not being…
FAST READ PORT FOR REGISTER FILE
Granted: August 16, 2007
Application Number:
20070189090
Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations. A pair of pull-down transistor stacks connected to memory cell latch loops allows a single selected pull-down stack of the pair to toggle a memory cell latch loop to a desired…
FAST READ PORT FOR REGISTER FILE
Granted: August 16, 2007
Application Number:
20070189092
Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations. A pair of pull-down transistor stacks connected to memory cell latch loops allows a single selected pull-down stack of the pair to toggle a memory cell latch loop to a desired…
FAST READ PORT FOR REGISTER FILE
Granted: August 16, 2007
Application Number:
20070189101
Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations. A pair of pull-down transistor stacks connected to memory cell latch loops allows a single selected pull-down stack of the pair to toggle a memory cell latch loop to a desired…
Reverse polish notation processing device, and electronic integrated circuit including such a processing device
Granted: August 16, 2007
Application Number:
20070192569
The disclosure relates to a reverse Polish notation processing device, allowing execution of a set of instructions wherein each instruction comprises N operands at most, where N?1. The device implements management of a stack whose size is variable. Such a device includes: a storage device including a random access memory and a cache memory; a stack pointer managing device for managing a stack pointer; and a contents managing device for managing the contents of the stages of the stack,…
Device for generation of a reference frequency and corresponding electronic circuit
Granted: August 2, 2007
Application Number:
20070176698
A device for generation of a reference frequency includes a component configured for generating a reference voltage, and a slaving circuit configured for slaving the reference frequency to the reference voltage.
Semiconductor array and method for manufacturing a semiconductor array
Granted: July 19, 2007
Application Number:
20070164443
Semiconductor array, with an element region (400), with a conductive substrate (100), with a buried insulation layer (200), which isolates the element region (400) from the conductive substrate (100), with at least one trench (700), which is filled with an insulation material (710) and which isolates at least one element (1000) in the element region (400) from other elements in the element region (400), with an electrical conductor (750), which is connected conductively to the…
MANUFACTURING OF SILICON STRUCTURES SMALLER THAN OPTICAL RESOLUTION LIMITS
Granted: July 19, 2007
Application Number:
20070166971
Method for forming silicon structures, such as upright gates or fins on a wafer substrate, particularly for use as a building block for semiconductor devices. The structures are smaller than can be resolved by conventional optical lithography. A plan of the area-wise dimensions of the fin or gate structure is mapped to a substrate as an ideal, Conductive and insulative layers are deposited onto the substrate and a work region that includes the desired structure is designed by…
DUAL-PROCESSOR COMPLEX DOMAIN FLOATING-POINT DSP SYSTEM ON CHIP
Granted: July 19, 2007
Application Number:
20070168908
A system for digital signal processing, configured as a system on chip (SoC), combines a microprocessor core and digital signal processor (DSP) core with floating-point data processing capability. The DSP core can perform operations on floating-point data in a complex domain and is capable of producing real and imaginary arithmetic results simultaneously. This capability allows a single-cycle execution of, for example, FFT butterflies, complex domain simultaneous addition and…
MICROPROCESSOR FOR EXECUTING BYTE COMPILED JAVA CODE
Granted: July 19, 2007
Application Number:
20070168954
A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal programming models, a Java model and a RISC model. The entities share a common data path and operate independently, although not in parallel. The microprocessor includes a combined register file in which the Java module sees the elements in the register file as a circular operand stack and the…
