Sense architecture
Granted: July 14, 2009
Patent Number:
7561485
A memory system is disclosed. In one embodiment, the memory system includes a first bitline, where the first bitline produces a first transient current. The memory system also includes a sense amplifier coupled to the first bitline. The memory system also includes a second bitline coupled to the sense amplifier, where the second bitline produces a second transient current that is equal to the first transient current. The sense amplifier enables the first and second transient currents to…
Low voltage non-volatile memory cell with electrically transparent control gate
Granted: June 30, 2009
Patent Number:
7554151
An EEPROM having a charge storage element, i.e., a floating gate, in the substrate adjacent to vertically separated source and drain electrodes. An electrically transparent poly control gate allows relatively low voltages to be used for program, erase, and read operations when a plurality of similar devices are arranged in a memory array. A second poly member, called a tunnel poly member, communicates with source and drain electrodes in synchronism with the poly control gate to provide…
Random number generator in a battery pack
Granted: June 30, 2009
Patent Number:
7554288
Apparatus, method and computer program product are provided for battery management. In one implementation, a method of communication provided. The method includes enabling determining when a battery pack is coupled to a device, the battery pack including a battery management system. The method also includes generating a random number at the battery management system, the battery management system including battery monitoring circuitry, a processor, memory and a random number generator.…
Randomizing current consumption in memory devices
Granted: June 30, 2009
Patent Number:
7554865
In some implementations, a memory device includes a plurality of memory cells, each memory cell storing a plurality of data bits; an input/output interface that is configured to, in response to receiving a read signal and an address value that identifies a specific memory cell in the plurality of memory cells, output a plurality of data bits corresponding to the identified specific memory cell; and a delay controller that is configured to delay the outputting to the input/output…
Packed add-subtract operation in a microprocessor
Granted: June 30, 2009
Patent Number:
7555514
A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom half-word locations of a designated destination register. The microprocessor includes an arithmetic-logic unit (ALU) with adder circuitry that can be selectively…
Method and circuit arrangement for synchronizing a function unit with a predetermined clock frequency
Granted: June 23, 2009
Patent Number:
7551702
A receiver is synchronized with a first clock frequency or signal of a transmitter for the proper reception of transmitted and received signals, such as data carrying signals (DS). The first clock frequency is for example a carrier frequency. A local oscillator generates a second clock frequency or signal in the receiver. Cycles or impulses of the second clock signal are counted between predetermined flanks of the received signal (DS) to provide a count (N). Based on the second clock…
Implementation of column redundancy for a flash memory with a high write parallelism
Granted: June 23, 2009
Patent Number:
7551498
A redundant memory array has r columns of redundant memory cells, r redundant senses, and a redundant column decoder. Redundant address registers store addresses of defective regular memory cells. Redundant latches are provided in n groups of r latches. Redundancy comparison logic compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal to disable the regular senses for one of the n groups…
Programmable clock generator apparatus, systems, and methods
Granted: June 23, 2009
Patent Number:
7551016
An apparatus and method for generating local clock signals from system clock signals based upon user inputs that provide a frequency multiplier and a frequency divider. The frequency multiplier and frequency divider are stored in an interface. System clock signals are received and local clock signals are generated by the circuitry. The frequency of the local clock signals is equal to the frequency of the system clock signals multiplied by the frequency multiplier and divided by the…
Logic cell with two isolated redundant outputs, and corresponding integrated circuit
Granted: June 23, 2009
Patent Number:
7550992
The disclosure relates to a logic cell for an integrated circuit, including two redundant outputs, a first output equipped with an output transistor of type P and a second output equipped with an output transistor of type N. Such a cell includes isolation element connecting the first and second outputs and forming an isolation resistance.
Method and circuit for a voltage supply for real time clock circuitry based on voltage regulated charge pump
Granted: June 23, 2009
Patent Number:
7550954
A versatile voltage regulator accommodates either an Alkaline or Lithium-Ion battery main battery and provides low-current power for a real time clock module and for charging a backup battery. Depending upon the battery power source that is used, the present invention provides a best circuit configuration for efficient power conversion. If the power converter according to the present invention provides a regulated output voltage that is greater than the main battery voltage of an…
Method for providing a nanoscale, high electron mobility transistor (HEMT) on insulator
Granted: June 23, 2009
Patent Number:
7550758
A method and resulting high electron mobility transistor comprised of a substrate and a relaxed silicon-germanium layer formed over the substrate. A dopant layer is formed within the relaxed silicon-germanium layer. The dopant layer contains carbon and/or boron and has a full-width half-maximum (FWHM) thickness value of less than approximately 70 nanometers. A strained silicon layer is formed over the relaxed silicon-germanium layer and is configured to act as quantum well device.
Means to deactivate a contactless device
Granted: June 16, 2009
Patent Number:
7548164
A method and apparatus for deactivating an identification device or RFID tag, such as an e-passport or an ID card that has been revoked, has expired, or is invalid. A programmable memory circuit is coupled to a controlling circuit that is coupled to a shorting circuit that may activate or deactivate the operation of the identification device.
System, apparatus and method for contaminant reduction in semiconductor device fabrication equipment components
Granted: June 2, 2009
Patent Number:
7540298
A system and apparatus for reducing contaminants of physical components (e.g., semiconductor device fabrication equipment components), featuring a manifold having a passageway in fluid communication with a plurality of inlets and for providing a purge fluid to removably connected components to undergo contaminant reduction. The inlets are coupled to a plurality of manifold valves to which components are removably connected. The manifold valves are operable to place connected components…
Process for producing a base connection of a bipolar transistor
Granted: June 2, 2009
Patent Number:
7541249
A process for producing a base connection of a bipolar transistor is provided. The process includes the steps of providing a semiconductor structure that can include a three-dimensional sacrificial structure that is selectively removable with respect to adjacent regions. A first semiconductor layer and a second layer of dielectric material is deposited. The first semiconductor layer is partially exposed by partial removal of the second layer. A first reaction layer is deposited that,…
Method for forming a self-aligned twin well region with simplified processing
Granted: June 2, 2009
Patent Number:
7541250
A method for forming a self-aligned twin well region is provided. The method includes implanting a first well type doping species into the DHL such that its distribution remains stopped in the DHL above the silicon substrate, etching away a portion of the DHL using a photoresist mask, implanting a second well type doping species into the portions of the silicon substrate exposed by the etching, and moving a portion of the first well type doping species into the silicon substrate.
Infrared receiver chip
Granted: May 26, 2009
Patent Number:
7538437
An infrared receiver chip is provided for installation in a standardized lead frame of an infrared receiver module having multiple contact areas for connection of associated function points of the lead frame via bond wires, wherein at least one contact area is spaced apart from the outer edge of the infrared receiver chip and all contact areas are positioned with respect to one another such that, when the infrared receiver chip is installed in any standardized lead frame, the respective…
Circuits to delay a signal from a memory device
Granted: May 26, 2009
Patent Number:
7539078
Various apparatus and methods include a clock circuit to receive a first clock signal to generate a second clock signal having a frequency different from a frequency of the first clock signal. A clock capturing circuit receives the second clock signal for determining a number of delay elements corresponding to an amount of a period of the second clock signal. A delay calculation circuit calculates an amount of time corresponding to the number of delay elements. And a delay circuit delays…
Circuit layout with active components and high breakdown voltage
Granted: May 26, 2009
Patent Number:
7539965
An integrated circuit layout having a first circuit connection, a second circuit connection, and active components is provided, whereby the active components each have an input connection and an output connection and a predefined maximum reverse voltage between the input connection and the output connection, and whereby a maximum value of a voltage swing, achieved between the first circuit connection and the second circuit connection, is greater than the predefined maximum reverse…
Integrated circuit with integrated circuit section to aid in testing
Granted: May 19, 2009
Patent Number:
7535245
An integrated circuit is disclosed having at least one digital input, which has a first circuit section that has a current-voltage characteristic and that in the absence of an input signal holds a voltage at the input at a defined value, and having a second circuit section that provides a signal that is internal to the circuit and whose state does not directly show itself at an output of the circuit. The first circuit section has a control input for a control signal and is designed to…
Operational amplifier
Granted: May 19, 2009
Patent Number:
7535300
An operational amplifier and use of an operational amplifier is provided that includes an input differential amplifier, which is connected to a first input and to a second input and a differential output stage, which is connected to the input differential amplifier and a first output and a second output. The differential output stage has a first branch with two first transistors, whose drain and/or collector are connected to one another and to the first output. The differential output…
