Cadence Design Systems Profile

Cadence Design Systems Patent Grants

Systems and methods for analyzing node impedance state

Patent Number 10318682 - June 11, 2019

Various embodiments provide for analyzing impedance states of a set of nodes in a circuit design and providing a set of reasons for those…

Balanced scaled-load clustering

Patent Number 10318693 - June 11, 2019

Aspects of the present disclosure address improved systems and methods for designing an integrated circuit design clock tree structure with…

Customizable built-in self-test testplans for memory units

Patent Number 10319459 - June 11, 2019

An exemplary memory arrangement can be provided, which can include, for example, a memory(ies), and an algorithmic memory unit(s) (AMU)…

Full-chip hierarchical inverse lithography

Patent Number 10310372 - June 4, 2019

According to certain aspects, the present embodiments relate to an inverse lithography technology (ILT) solution that provides masks with…

Method and system to mitigate large power load steps due to intermittent execution in a computation system

Patent Number 10303230 - May 28, 2019

Disclosed herein are systems and methods to generate, by a compiling processor, one or more sets of one or more execution instructions…

Cadence Design Systems Patent Applications

Systems And Methods For Binding Mismatched Schematic And Layout Design Hierarchy

Application Number 20170124235 - May 4, 2017

Disclosed herein are systems and methods that allow a layout editor function, presented in a graphical user interface, of an EDA, to indicate…

SYSTEM AND METHOD FOR IMPLEMENTING AND VALIDATING STAR ROUTING FOR POWER CONNECTIONS AT CHIP LEVEL

Application Number 20160210393 - July 21, 2016

A system, method, and computer program product for automating the design and routing of non-shared one-to-many conductive pathways between a…

METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING HIGH CURRENT CARRYING INTERCONNECTS IN ELECTRONIC DESIGNS

Application Number 20160070841 - March 10, 2016

Various embodiments implement additional connectivity for electronic designs by identifying one or more regions for a route in normal…

METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR SCHEMATIC DRIVEN, UNIFIED THERMAL AND ELECTROMAGNETIC INTERFERENCE COMPLIANCE ANALYSES FOR ELECTRONIC CIRCUIT DESIGNS

Application Number 20160063171 - March 3, 2016

Disclosed are methods and systems for by identifying or generating an electrical schematic, generating a thermal schematic by associating…

DEBUGGING SESSION HANDOVER

Application Number 20140281730 - September 18, 2014

A method includes, during operation of a software debugging tool on a software program, and upon indication by a first user of the software…

Cadence Design Systems Federal District Court Decisions

Cadence Design Systems, Inc. v. Pounce Consulting, Inc.

California Northern District Court - April 22, 2019

ORDER ADOPTING MAGISTRATE JUDGE'S REPORT AND RECOMMENDATION by Judge Phyllis J. Hamilton. (pjhlc2S, COURT STAFF) (Filed on 4/22/2019)

Cadence Design Systems, Inc. v. Pounce Consulting, Inc.

California Northern District Court - January 30, 2019

ORDER RE ENTRY OF DEFAULT. Signed by Judge Phyllis J. Hamilton on 1/30/2019. (pjhlc2S, COURT STAFF) (Filed on 1/30/2019)

Cadence Design Systems, Inc. v. Pounce Consulting, Inc.

California Northern District Court - December 14, 2018

ORDER RE MOTION TO WITHDRAW AS COUNSEL by Judge Phyllis J. Hamilton. (pjhlc2S, COURT STAFF) (Filed on 12/14/2018)

Cadence Design Systems, Inc. v. Pounce Consulting, Inc.

California Northern District Court - December 13, 2018

ORDER re 194 STIPULATION WITH PROPOSED ORDER re Document Production filed by Cadence Design Systems, Inc. Signed by Judge Elizabeth…

Cadence Design Systems, Inc. v. Pounce Consulting, Inc. et al

California Central District Court - October 22, 2018

ORDER GRANTING PLAINTIFF CADENCE DESIGN SYSTEMS, INC.'S UNOPPOSED MOTION TO COMPEL (ECF 1 , 12 ) by Magistrate Judge Steve Kim. This…