METHOD AND SYSTEM TO FACILITATE REVIEW OF SCHEMATICS FOR AN ELECTRONIC DESIGN
Granted: January 4, 2024
Application Number:
20240005081
Disclosed is a method and system for visualizing schematic changes for an electronic design, where multiple schematic view interfaces are provided such that a first schematic interface displays an older schematic version and a second schematic interface displays a newer schematic version. Coordination is performed between the multiple schematic views such that an element within any of the first or second schematic views is appropriately highlighted based upon a user input.
METHOD AND APPARATUS FOR DETERMINING WAIVER APPLICABILITY CONDITIONS AND APPLYING THE CONDITIONS TO MULTIPLE ERRORS OR WARNINGS IN PHYSICAL VERIFICATION TOOLS
Granted: May 7, 2020
Application Number:
20200143100
An approach is described for determining waiver applicability conditions and applying the conditions to multiple errors or warnings in physical verification tools. According to some embodiments, the approach includes identification of a waiver of an error or warning, registration of one or more condition sets for waiver of an error or warning, waiver of multiple errors or warnings that match the registered one or more condition sets, and further comprise any or all of the following:…
Systems And Methods For Binding Mismatched Schematic And Layout Design Hierarchy
Granted: May 4, 2017
Application Number:
20170124235
Disclosed herein are systems and methods that allow a layout editor function, presented in a graphical user interface, of an EDA, to indicate certain layout instances or “cell views” as “transparent.” The instances are indicated as transparent using various layout editor commands or layout designer markers. Unlike conventional solutions, a binder within the layout editor of the EDA is not required to bind layout transparent instances to corresponding instances in a related…
SYSTEM AND METHOD FOR IMPLEMENTING AND VALIDATING STAR ROUTING FOR POWER CONNECTIONS AT CHIP LEVEL
Granted: July 21, 2016
Application Number:
20160210393
A system, method, and computer program product for automating the design and routing of non-shared one-to-many conductive pathways between a common pad and circuit blocks in an integrated circuit. Such pathways are routinely required for power and signal distribution purposes. Automated scripts perform a star routing methodology and validate the routing results. The methodology processes input width and layer constraints and from-to's denoting start and end points for each route by…
METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING HIGH CURRENT CARRYING INTERCONNECTS IN ELECTRONIC DESIGNS
Granted: March 10, 2016
Application Number:
20160070841
Various embodiments implement additional connectivity for electronic designs by identifying one or more regions for a route in normal connectivity of an electronic design, identifying a plurality of seeding segments from the route based at least in part upon the one or more regions, identifying a plurality of additional nodes in the plurality of seeding segments, and generating one or more additional routes connecting the plurality of additional nodes in the plurality of seeding…
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR SCHEMATIC DRIVEN, UNIFIED THERMAL AND ELECTROMAGNETIC INTERFERENCE COMPLIANCE ANALYSES FOR ELECTRONIC CIRCUIT DESIGNS
Granted: March 3, 2016
Application Number:
20160063171
Disclosed are methods and systems for by identifying or generating an electrical schematic, generating a thermal schematic by associating thermal RC circuits of the electronic design with the electrical schematic, performing at least two analyses of an electrical analysis, a thermal analysis, and an electromagnetic interference compliance (EMC) analysis with the electrical schematic and the thermal schematic of the electronic design. The electrical, thermal, and EMC analyses may be…
METHOD AND SYSTEM FOR DEBUGGING A PROGRAM
Granted: September 18, 2014
Application Number:
20140282415
A computer-implemented method and system for debugging a program is disclosed. The method may include obtaining data on inter-component calls of a call chain of an execution run of the program between segments of Multilanguage software components of the program, the data relating to the identity of the Multilanguage software components in which these segments are included and an order in which the segments are called in the call chain. The method may further include obtaining a user…
METHOD AND SYSTEM FOR DEBUGGING OF A PROGRAM
Granted: September 18, 2014
Application Number:
20140282414
A computer implemented method for debugging of a program may include parsing a code segment of the program, the code segment invoking one or a plurality of execution events during an execution of the program to derive a plurality of questions, each relating to an execution event of said one or a plurality of execution events, based on the parsing of the code segment and on information recorded during the execution of the program. The method may also include selecting one of the questions…
DEBUGGING SESSION HANDOVER
Granted: September 18, 2014
Application Number:
20140281730
A method includes, during operation of a software debugging tool on a software program, and upon indication by a first user of the software debugging tool of a step of the operation as a event of interest, collecting data related to that event of interest. A unique identifier is assigned to the collected data. Access to the collected data is enabled for a second user of the software debugging tool.
DESIGN SYNTHESIS OF CLOCK GATED CIRCUIT
Granted: September 11, 2014
Application Number:
20140258948
Technology for synthesizing a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the circuit's behavior, or other functionality, via multiple statements, including a conditional statement. The technology includes analyzing statements upstream and/or downstream from the conditional statement, identifying one or more statements having dependency relationships with the conditional…
FINITE-STATE MACHINE ENCODING DURING DESIGN SYNTHESIS
Granted: September 11, 2014
Application Number:
20140258947
Technology for finite-state machine (FSM) encoding during design synthesis for a circuit is disclosed. The encoding of the FSM may include determining values of a multi-bit state register that are to represent particular states of the FSM. These values may be determined based on possible states of the FSM, possible transitions between the states, probabilities of particular transitions occurring, amounts of false switching associated with particular transitions, area estimates for logic…
METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH SIMULATION AWARENESS
Granted: August 21, 2014
Application Number:
20140237440
Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or…
METHOD AND APPARATUS FOR DERIVED LAYERS VISUALIZATION AND DEBUGGING
Granted: July 31, 2014
Application Number:
20140215422
A computer-implemented method, system and computer program product for visualizing derived layer shapes of an integrated circuit design are disclosed. The computer-implemented method, system and computer program product include visualizing the derived layer shapes on a layout canvas; providing a step by step process for visualizing each derived layer shape as each derived layer shape is generated; and providing a hierarchy of intermediate derived layers based upon the step by step…
Method and Apparatus for Verifying Debugging of Integrated Circuit Designs
Granted: June 19, 2014
Application Number:
20140173541
Method and apparatus for verifying debugging aspects of integrated circuit (IC) designs. In one aspect, an IP provider(s) can use the same process that isolated IP defect(s) to demonstrate to the customer (whether an IC designer or an IP consumer such as a smartphone manufacturer) that the debugging was successful, and that errors in operation will not recur. In another aspect, the invention provides a facility that enables the IP provider to demonstrate to an IP consumer that a repaired…
Method and Apparatus for Isolating and/or Debugging Defects in Integrated Circuit Designs
Granted: June 19, 2014
Application Number:
20140173539
Method and apparatus for debugging aspects of integrated circuit (IC) designs employ techniques by which defective intellectual property (IP) in those IC designs can be exercised, and defects identified, without disturbing the IP itself, but at the same time isolating the source of the defect(s) to the responsible IP provider(s). The IP provider then can debug the IP. In one aspect, the techniques give the IP provider(s) specific information about the nature of the defect, facilitating…
GENERATION OF A RANDOM SUB-SPACE OF THE SPACE OF ASSIGNMENTS FOR A SET OF GENERATIVE ATTRIBUTES FOR VERIFICATION COVERAGE CLOSURE
Granted: June 19, 2014
Application Number:
20140172347
System, method and computer readable medium are described. The method may include obtaining user defined distribution traits characterizing a random sub-space of a space of assignments for a set of generative variables. The method may further include applying the user defined distribution traits on the space of assignments for a set of generative variables to generate the random sub-space of the space of assignments for a set of generative variables. The method may also include testing a…
PRODUCING A NET TOPOLGY PATTERN AS A CONSTRAINT UPON ROUTING OF SIGNAL PATHS IN AN INTEGRATED CIRCUIT DESIGN
Granted: May 1, 2014
Application Number:
20140123094
A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent…
GENERATING AN EQUIVALENT WAVEFORM MODEL IN STATIC TIMING ANALYSIS
Granted: April 3, 2014
Application Number:
20140096099
A method is provided for use during static timing analysis of an integrated circuit design to produce an equivalent waveform model, the method comprising: using an analog model of the inner component, to simulate an inner component to produce multiple analog simulation output characterization waveforms as a function of multiple input waveforms used to characterize the design cell; using the analog model of the inner component to simulate the inner component to produce an analog…
Method and Apparatus for Optimizing Memory-Built-In-Self Test
Granted: March 27, 2014
Application Number:
20140089874
Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an…
Method and Apparatus for Optimizing Memory-Built-In-Self Test
Granted: March 27, 2014
Application Number:
20140089875
Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an…
