Control algorithm generator for non-volatile memory module
Granted: April 23, 2024
Patent Number:
11966633
An NVM algorithm generator that evaluates a Liberty file characterizing an NVM module and a memory view of the NVM module that identifies ports and associated operations of the NVM module to generate a control algorithm. The control algorithm includes a read algorithm that includes an order of operations for assigning values to ports of the NVM module to assert a read condition of a strobe port, executing a memory read on the NVM module and setting values to the ports on the NVM module…
Method and system to implement a composite, multi-domain model for electro-optical modeling and simulation
Granted: April 16, 2024
Patent Number:
11960809
Provided is an improved method, system, and computer program product to implement simulation for photonic devices. A composite, multi-domain simulation model is disclosed, with connected domain-specific representations that allow the use of the most relevant simulator technology for a given domain. The model has external connection points either expressed as actual ports or virtual ones, embodied by simulator API calls in the model.
Managing multiple cache memory circuit operations
Granted: April 16, 2024
Patent Number:
11960400
A cache memory circuit capable of dealing with multiple conflicting requests to a given cache line is disclosed. In response to receiving an acquire request for the given cache line from a particular lower-level cache memory circuit, the cache memory circuit sends probe requests regarding the given cache line to other lower-level cache memory circuits. In situations where a different lower-level cache memory circuit is simultaneously trying to evict the given cache line at the particular…
System and method for poison information propagation in a storage device
Granted: April 16, 2024
Patent Number:
11960351
Systems and methods for propagating poison information are provided. Embodiments include receiving write data having a poison flag asserted indicating the data to be written to a memory device is erroneous. Embodiments further include converting the write data to a pre-fixed data pattern and generating a parity code, based upon, at least in part, the pre-fixed data pattern. Embodiments may also include injecting a correctable error into the write-data or parity code and writing the write…
Test-point flop sharing with improved testability in a circuit design
Granted: April 2, 2024
Patent Number:
11947887
A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that is configured to evaluate the circuit netlist to determine compatibility of the test-point nodes in the circuit netlist. The test-point flop allocation module can further allocate each of the test-point flops to a…
Providing concise data for analyzing checker completeness
Granted: March 26, 2024
Patent Number:
11941335
Methods and systems for providing concise data for analyzing checker completeness, in the context of formal verification analysis of circuit designs. The methods and systems concisely report information useful to a human user (e.g., circuit designer or verification engineer) for efficiently determining what manual action should be taken next to resolve holes in verification coverage. The reported information can include lists of signals on which checkers can be written, which lists can…
System and method for intelligent intent recognition based electronic design
Granted: March 26, 2024
Patent Number:
11941334
Embodiments include herein are directed towards a system and method for intelligent intent recognition based electronic design. Embodiments may include receiving, using a processor, a natural language input from a user at an intent recognition model. Embodiments may also include performing intent recognition on the natural language input at the intent recognition model and providing an output from the intent recognition model to a command generator. Embodiments may further include…
Direct-switching h-bridge current-mode drivers
Granted: March 19, 2024
Patent Number:
11936353
A current-mode transmitter amplifies a differential input signal to a differential, current-mode output signal. A split-input, current-mode-logic stage produces small, analog signals to limit switching currents and thus power consumption and power-supply noise. These small, analog signals are driven through a source-follower stage to reduce loading and shift the common-mode voltage to a desired level. A switched-current-source H-bridge driver combines differential outputs from the…
Efficient storage of error correcting code information
Granted: March 19, 2024
Patent Number:
11934269
Multiple independent point-to-point memory channels are operated, by at least one controller, in parallel to form a wider memory channel. The memory components on these point-to-point channels include the ability to connect to multiple (e.g., 2) instances of these independent memory channels. The controller operates multiple instances of the wider channels with the memory components configured in a clamshell mode. A single memory component is also operated in clamshell mode to provide…
System, media, and method for deep learning
Granted: March 12, 2024
Patent Number:
11928582
Embodiments of the invention provide a system, media, and method for deep learning applications in physical design verification. Generally, the approach includes maintaining a pattern library for use in training machine learning model(s). The pattern library being generated adaptively and supplemented with new patterns after review of new patterns. In some embodiments, multiple types of information may be included in the pattern library, including validation data, and parameter and…
Multi-threaded network routing based on partitioning
Granted: March 12, 2024
Patent Number:
11928500
Various embodiments provide for multi-threaded network routing of a circuit design based on partitioning networks of the circuit design, which can enable partitioning routing tasks for the circuit design. More particularly, some embodiments iteratively partition networks of a circuit design into groups of networks, which enable various embodiments to schedule routing tasks for those groups of networks to available threads such that no two networks of the circuit design with overlapping…
Formal analysis methods for debug compilation
Granted: March 12, 2024
Patent Number:
11928410
Methods and systems are disclosed for optimizing compilation efforts for design debug based on formal analyses. The method includes accessing a circuit design, automatically determining a segment as being a design region of interest, identifying a behavior within the segment for performing at least one verification test, compiling the segment without compiling a remainder of the circuit design, and providing performance indicators corresponding to the behavior within the segment based on…
System and method for non-intrusive debugging at an embedded software breakpoint
Granted: March 12, 2024
Patent Number:
11928045
The present disclosure relates to a method for use with an electronic design. Embodiments may include simulating a processor model and a hardware model, each executed with a corresponding simulator thread on a simulation platform. Embodiments may also include simulating embedded software using the processor model. The simulating may include updating a given register of the processor model that stores a value that changes in response to switching between processes within the embedded…
System and method for error checking and correction with metadata storage in a memory controller
Granted: March 12, 2024
Patent Number:
11928027
Embodiments include receiving fixed size error checking and correction data blocks and metadata at a memory controller. Embodiments may include performing data to symbol mapping based upon the fixed size data blocks and providing an output of the data to symbol mapping to a first encoder without metadata configured for full detection correction of single device error and to a second encoder with metadata configured for partial detection correction of single device error. Embodiments may…
Read eye training
Granted: February 20, 2024
Patent Number:
11909565
Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. In embodiment, a single-ended receiver trains DFE coefficients and the slicer reference voltage to improve the received eye height. The process for training avoids many whole range sweeps thereby shortening training time. A custom data pattern that includes low-frequency (DC with respect to DFE) and high-frequency (AC…
Emulation system supporting representation of four-state signals
Granted: February 13, 2024
Patent Number:
11900135
An emulation processor may be configured to support emulating unknown binary logic based on non-arbitrariness of the unknown binary logic. For example, an unknown binary logic signal may take the finite binary values of 0 and 1. The circuitry in the emulation processor is configured to generate and propagate outputs based on the interactions of known input binary signals with the unknown input binary signals having non-arbitrary states. The emulation processor may support the both…
Emulation system supporting representation of four-state signals
Granted: February 13, 2024
Patent Number:
11900135
An emulation processor may be configured to support emulating unknown binary logic based on non-arbitrariness of the unknown binary logic. For example, an unknown binary logic signal may take the finite binary values of 0 and 1. The circuitry in the emulation processor is configured to generate and propagate outputs based on the interactions of known input binary signals with the unknown input binary signals having non-arbitrary states. The emulation processor may support the both…
Diagnosing multicycle transition faults and/or defects with AT-speed ATPG test patterns
Granted: February 6, 2024
Patent Number:
11892501
An integrated circuit (IC) test engine generates N-cycle at-speed test patterns for testing for candidate faults and/or defects of a first set of transition faults and/or defects of an IC design. A diagnostics engine that receives test result data characterizing application of the N-cycle at-speed test patterns to a fabricated IC chip based on the IC design by an ATE, in which the test result data includes a set of miscompare values characterizing a difference between an expected result…
System and method for routing in an electronic design
Granted: February 6, 2024
Patent Number:
11893335
Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include receiving a selection of an instance associated with an electronic design at an electronic design schematic displayed on a graphical user interface. Embodiments may also include selecting a corresponding instance within an electronic design layout displayed on a graphical user interface. Embodiments may further include receiving a selection of a source topology and routing at…
Method and system for debugging metastability in digital circuits
Granted: February 6, 2024
Patent Number:
11892504
Systems and methods of debugging a design under test for metastability issues using formal verification. In one aspect, the method includes determining, by a server, that a functionality of the DUT failed an assertion; generating, by the server, a plurality of first waveforms for a plurality of clock domain crossing (CDC) pairs that are in a cone of influence of the assertion; applying, by the server, a constraint including a condition to the plurality of waveforms; and generating, by…
