Interface device
Granted: January 28, 2025
Patent Number:
12212315
Methods and systems are provided for transmitting data using thin-oxide devices. The methods and system generate a first bias voltage and a second bias voltage based on a power supply voltage of the second voltage domain, the first bias voltage value representing a high-level voltage signal of the first voltage domain, and the second bias voltage representing a low-level voltage signal of the second voltage domain and its value corresponds to a difference between the second voltage…
Wireline receiver sampling circuit
Granted: January 21, 2025
Patent Number:
12206532
Embodiments included herein are directed towards sampling circuits and methods of using the same. Embodiments may include a data sense amplifier circuit and a reference sense amplifier circuit directly connected with the data sense amplifier circuit. Embodiments may further include a latch circuit configured to receive a first input from the data sense amplifier circuit and a second input from the reference sense amplifier circuit. The latch circuit may be further configured to generate…
Read data strobe path having variation compensation and delay lines
Granted: January 21, 2025
Patent Number:
12205673
Various embodiments described herein provide for a read data strobe (RDQS) path having variation compensation (e.g., voltage and temperature compensation), delay lines, or both, where the RDQS path can be included by a physical (PHY) interface for a memory device, such as a Double Data Rate (DDR) Dynamic Random-Access Memory (DRAM) memory device.
System and method for verifying a cross-connection of lanes in a multi-lane environment using a single testbench
Granted: January 21, 2025
Patent Number:
12204423
An approach for verifying a cross-connection of lanes in a multi-lane environment using a single testbench-is provided. The approach may include providing a physical receiver lane index associated with a local device and providing a physical transmitter lane index associated with a peer device. The approach may further include randomizing a number of connected receiver lanes associated with the local device and a number of connected receiver lanes associated with the peer device. The…
High accuracy timestamping of transmissions at physical layer of communication devices and systems
Granted: January 14, 2025
Patent Number:
12199770
A method can include obtaining, at a physical communication layer integrated with a communication interface, a data packet, detecting, by a detection circuit integrated with the physical communication layer, a portion of data in the data packet corresponding to a marker identifying the data packet, linking, by the physical communication layer based on the marker, a timestamp with the data packet, and transmitting, by the physical communication layer, the data packet linked with the…
System and method for creating a high-level parameter relational data model for memory configurability solutions
Granted: December 31, 2024
Patent Number:
12182020
Embodiments are directed towards a method for creating a relational memory designed for one or more key parameters in at least one memory part configurations library. The method may include identifying one or more high-level parameters (HLPs) within the at least one memory part configurations library, assigning each non-HLP parameter an HLP key, using the assigned HLP keys as a frame of reference to cross-correlate each non-HLP parameter with every other non-HLP parameter in the at least…
Clock duty cycle measurement
Granted: December 31, 2024
Patent Number:
12184286
The present disclosure describes a circuit that may include a first amplifier portion configured to receive a first input signal corresponding to a first clock signal and a second input signal corresponding to a second clock signal. The circuit may include a first amplifier of the first amplifier portion. The first amplifier may be configured to receive a first amplifier input signal and a second amplifier input signal. The circuit may include a second amplifier portion configured to…
System and method for write clock double data rate duty cycle correction
Granted: December 31, 2024
Patent Number:
12183427
The present disclosure relates to a system and method for duty cycle correction is provided. The method may include receiving a signal at a duty cycle adjuster and performing serializer clock duty cycle correction at the duty cycle adjuster. The method may further include performing true clock duty cycle correction at a transmitter duty cycle adjuster and performing complementary duty cycle distortion correction at the transmitter duty cycle adjuster.
Systems and methods for exporting design data using near-optimal multi-threading scheme
Granted: December 31, 2024
Patent Number:
12182613
A system for generating a single design data file may include a processor and a memory. The processor may obtain design data including a plurality of design units. The processor may determine a first order of the plurality of design units. The processor may translate each of the plurality of design units into a corresponding file fragment by executing multiple threads of a first process. The processor may aggregate each of the plurality of file fragments into the single design data file…
Embedded processor architecture with shared memory with design under test
Granted: December 31, 2024
Patent Number:
12182485
A shared memory is provided between simulation processors and emulation processors within an emulation chip. The shared memory is configured to enable the simulation processors and the emulation processors to exchange simulation data and emulation data respectively with each other during simulation and emulation operations. The simulation processors and the emulation processors may update their respective simulation and emulation operations in response to the simulation data and the…
Memory circuit with power registers
Granted: December 31, 2024
Patent Number:
12182016
A memory circuit may include both an array circuit and multiple register circuits, where the power to retrieve data from one of the register circuits may be less than the power to retrieve data from the array circuit. The array circuit may store multiple data words, and the multiple register circuits may be configured to store a subset of the multiple data words. During a first cycle, a read command and an address may be received. In response to a determination that the address…
Fragmented periodic timing calibration
Granted: November 26, 2024
Patent Number:
12153528
Periodic signal timing calibration is implemented in time-distributed fragments executed concurrently with occasional system-idling maintenance operations to maintain reliable synchronous communication between interconnected system components without impacting system availability.
Method and system for tracing and identifying target signals by cross-correlation to a signal pattern for a circuit
Granted: November 12, 2024
Patent Number:
12141514
Implementations can include a system to trace and identify target signals by cross-correlation to a signal pattern for a circuit, the system including a data processing system including memory and one or more processors to identify a target signal among a plurality of signals propagating through a circuit, detect one or more reference signals associated with an input to the target signal, the reference signals satisfying a threshold based on a depth associated with the target signal and…
Method, product, and system for universal verification methodology (UVM) sequence selection using machine learning
Granted: November 12, 2024
Patent Number:
12141512
An approach is disclosed herein to sequence selection in a UVM environment. Generally, this approach includes a training phase for each machine learning model of a plurality of machine learning models. Each model is trained to achieve a particular target state and is rewarded when a selected action or sequence of actions causes movement that might be beneficial to achieving that target state. Once a respective model is trained, the trained model can then be used to determine which one…
Queue circuit for controlling access to a memory circuit
Granted: November 12, 2024
Patent Number:
12141474
A queue circuit that manages access to a memory circuit in a computer system includes multiple sets of entries for storing access requests. The entries in one set of entries are assigned to corresponding sources that generate access requests to the memory circuit. The entries in the other set of entries are floating entries that can be used to store requests from any of the sources. Upon receiving a request from a particular source, the queue circuit checks the entry assigned to the…
Method, system, and computer program product for characterizing an electronic circuit using model order reduction-based envelope fourier techniques
Granted: November 12, 2024
Patent Number:
12141233
Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with an MOR-based envelope Fourier technique. Multiple training models may be determined at multiple time points for an electronic circuit by using at least the MOR-based envelope Fourier technique that comprises a harmonic balance technique. A training model of the multiple training models may be reduced into a reduced order training model in a reduced order space at least by applying at…
Extended-burst write training
Granted: October 15, 2024
Patent Number:
12119080
A control component transmits a timing strobe and associated write data burst to a memory component, extending the write data burst to include a quantity of successive bits in excess of active edges in the timing strobe to ensure that the write data burst is sampled under worst-case timing skew conditions.
Prefetch circuit for cache memory
Granted: October 8, 2024
Patent Number:
12111765
A prefetch circuit coupled to a cache memory circuit includes a storage circuit that stores multiple virtual-to-physical address map entries. In response to receiving an indication of a miss for an access request to the cache memory circuit, the prefetch circuit generates a prefetch address and compares it to a demand address included in the access request. In response to determining that the demand address and the prefetch address are in different memory pages, the prefetch circuit…
Port generation based on layout connectivity information
Granted: October 1, 2024
Patent Number:
12106032
Various embodiments provide for port generation for a circuit design based on layout connectivity information, which can be used as part of an automatic or a semi-automatic process of an electronic design automation (EDA) system. For instance, various embodiments access connectivity information for one or more networks of a circuit design, and use the connectivity information to identify pins of signal networks as positive connections for ports, and geometric shapes on references…
Thin-oxide voltage level shifter
Granted: October 1, 2024
Patent Number:
12107578
Methods and systems are provided for performing voltage level shifting using thin-oxide devices. The methods and systems convert an input signal associated with a first voltage domain to output signals associated with the first and second voltage domains. A first set of thin-oxide devices generate a first output signal at the high-level voltage signal when the input signal comprises a high logic level and generate the first output signal at a ground level voltage signal when the input…
