Cadence Design Systems Patent Grants

Method and system for debugging a system on chip under test

Granted: October 17, 2017
Patent Number: 9792402
A method for debugging a system on chip (SoC) under test, the method may include executing a test code on the SoC, the test code designed to invoke a plurality of actions; recording output data from the SoC resulting from the executed test code; linking between actions detected in the recorded output data and actions of the plurality of actions of the test code by identifying a start and an end times of each of the detected actions in the recorded output data, and associating the…

Method, system, and computer program product for schematic driven, unified thermal and electromagnetic interference compliance analyses for electronic circuit designs

Granted: October 10, 2017
Patent Number: 9785141
Disclosed are methods and systems for by identifying or generating an electrical schematic, generating a thermal schematic by associating thermal RC circuits of the electronic design with the electrical schematic, performing at least two analyses of an electrical analysis, a thermal analysis, and an electromagnetic interference compliance (EMC) analysis with the electrical schematic and the thermal schematic of the electronic design. The electrical, thermal, and EMC analyses may be…

System and method for evaluating spanning trees

Granted: October 10, 2017
Patent Number: 9785738
The present disclosure relates to a system and method for evaluating spanning trees. Embodiments may include receiving, using at least one processor, a spanning tree including one or more sinks coupled by one or more edges. Embodiments may further include receiving a user-selected floating parameter. Embodiments may also include interchanging the one or more edges of the spanning tree based upon, at least in part, the user-selected floating parameter.

System and method for fluid parameterized cell evaluation

Granted: October 10, 2017
Patent Number: 9785739
The present disclosure relates to a system and method for fluid parameterized cell (Pcell) evaluation. Embodiments may include displaying a fluid Pcell in a first format. Embodiments may further include identifying a first state in a fluid Pcell evaluation code. In some embodiments, the first state may indicate that alterations are being made to the fluid Pcell. Embodiments may also include displaying instances of the fluid Pcell in a second format based upon, at least in part,…

Harmonic balance analysis memory usage estimation

Granted: October 3, 2017
Patent Number: 9779188
Aspects of the present invention provide a system and method to estimate the amount of memory a harmonic balance analysis will require by measuring the memory allocated for a circuit database for a circuit undergoing harmonic balance analysis, determining the problem size of the harmonic balance analysis based on the information in the database, calculating the amount of memory for matrices, solution and auxiliary vectors needed for the harmonic balance analysis, and estimating the…

Methods, systems, and computer program product for implementing electronic design layouts with symbolic representations

Granted: October 3, 2017
Patent Number: 9779193
Disclosed are techniques for implementing electronic design layouts with symbolic representations. These techniques determine an abstraction scope of a layout circuit component in a layout of an electronic design by referencing a user input or one or more default settings of the abstraction mechanism and identify first data that are included in or associated with a schematic symbol for the layout circuit component by traversing data from a symbolic representation data source with…

Power shutdown with isolation logic in I/O power domain

Granted: September 26, 2017
Patent Number: 9772668
A circuit for that includes isolation logic is disclosed. In one aspect, circuit comprises at least one input/output (I/O) cell, the I/O cell further including circuitry functions, isolation control logic, and a capability to receive power to the I/O cell from a power domain source. In a second aspect an integrated circuit comprises a physical layer (PHY) logic and at least one input/output (I/O) cell in communication with the PHY logic. The I/O cell capable of receiving power from a…

Methods, systems, and articles of manufacture for implementing coplanar waveguide transmission lines in electronic designs

Granted: September 26, 2017
Patent Number: 9773086
Disclosed are techniques for implementing coplanar waveguide transmission lines in an electronic design. These techniques identify one or more electrically conductive shapes and a plurality of edge segments thereof in an electronic design. A plurality of model trace segments may be constructed based in part or in whole upon a plurality of edge segments. One or more coupled line groups may be generated with the plurality of model trace segments and one or more actual trace segments for a…

Method, system, and computer program product for improving mask designs and manufacturability of electronic designs for multi-exposure lithography

Granted: September 19, 2017
Patent Number: 9767245
Methods and systems for enhancing electronic designs for improving mask designs and manufacturability of electronic circuit designs for multi-exposure lithography are disclosed. The methods identify gap rectangles in a design and create gap blocks with the some of the identified gap rectangles according to at least their positions in a design and design rules. A relation graph is determined among the gap blocks or gap rectangles. The methods adjust some gap blocks by altering their sizes…

Methods and devices for high-sensitivity memory interface receiver

Granted: September 19, 2017
Patent Number: 9767888
Embodiments relate to systems, methods and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a first resistor connected to a first receiver input, four N-type metal oxide semiconductor (NMOS) field effect transistors (FETs), two PMOS FETS, and a trans-impedance amplifier wherein an input terminal of the trans-impedance amplifier is connected to a drain terminal of the second NMOS FET. Additional embodiments…

Apparatus and method for collaborative adaptation of hierarchically-designed schematics to variant design requirements

Granted: September 12, 2017
Patent Number: 9760666
A planned schematic for an electronic system is hierarchically divided into base-level schematic blocks which may be designed individually. In accordance with a plurality of sets of design requirements, variant overlays are designed for each base-level schematic block, each overlay including variant parameter values which may replace corresponding parameter values of the schematic blocks. The schematic blocks are integrated to generate a system-level schematic, and the variant overlays…

Method, system, and computer program product for implementing prototyping and floorplanning of electronic circuit designs

Granted: September 12, 2017
Patent Number: 9760667
Methods and systems for implementing prototyping and floorplanning for electronic circuit designs are disclosed. The method identifies or generates a representation of a design, modifies or updates the representation by moving a circuit component in the representation. The representation may be characterized in the pre-placement or post-placement stage to determine or identify distance constraints constraining object pairs in the representation. The method performs a timing and/or…

System and method for accelerated graphic rendering of design layout having variously sized geometric objects

Granted: September 12, 2017
Patent Number: 9761204
A system and method are provided for accelerated graphic rendering a view of a design layout view represented by a plurality of graphic objects defined by respective geometry data therefor. A database stores the geometry data having location and geometric portions. A large object module actuates retrieval of the geometry data for each of the graphic objects within the view selectively classified to be a large object. A small object module actuates partial retrieval of the geometry data…

Method and apparatus for extending and measuring phase difference between signals

Granted: September 12, 2017
Patent Number: 9762378
A phase difference multiplier circuit is disclosed that includes first and second delay circuits to apply two different quantities of delay to first and second input signals. The first and second delay circuits may operate in a first mode where a first and smaller amount of delay is imparted to the respective input signals. The first and second input signals differ in phase, and a transition in the first signal will be followed by a similar transition in the second signal. Following the…

Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniques

Granted: September 5, 2017
Patent Number: 9754072
One aspect checks and prepares design data (202) based on design rule(s) to identify tracks for physical implementation of an electronic design. Structured physical implementation (204) is performed to implement at least a part of the electronic design by using the tracks under separate design rule(s). Structured physical implementation using the tracks under separate design rules result in correct-by-construction implementation results automatically satisfying the design rule(s),…

Voltage stress tolerant high speed memory driver having flying capacitor circuit

Granted: September 5, 2017
Patent Number: 9754646
Embodiments relate to circuits, electronic design automation (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices operating on a core supply voltage to drive memory devices operating on a different supply voltage using low power and high data rates while avoiding voltage over-stress of thin-oxide transistors. In an embodiment, channels of a thin-oxide PMOS transistor, a thick-oxide PMOS transistor, a thick-oxide NMOS transistor, and a thin-oxide…

Method and system for triple patterning technology (TPT) violation detection and visualization

Granted: August 22, 2017
Patent Number: 9740814
A method, system, and computer program product for triple patterning technology (TPT) violation detection and visualization within an integrated circuit design layout are disclosed. In a first aspect, the method comprises mapping a plurality of violations of the integrated circuit design layout to a graph, generating a color graph corresponding to the graph, detecting at least one TPT violation from the color graph; and visualizing the at least one TPT violation on a layout canvas. In a…

Method and apparatus for efficient generation of compact waveform-based timing models

Granted: August 8, 2017
Patent Number: 9727676
For a circuit path to be represented in a timing model, a set of propagating waveforms substantially converges through waveform stabilization to a uniform waveform at a waveform invariant node and all pins following. The circuit path is decomposed at the waveform invariant node into first and second portions, which are characterized as first and second timing arcs. In computing output slew and delay values, the first timing arc generation factors only a single output load of the waveform…

Multiprocessing subsystem with FIFO/buffer modes for flexible input/output processing in an emulation system

Granted: August 1, 2017
Patent Number: 9721048
In a system and method for emulating a circuit design, an emulation system receives input instructions from a host device executing the emulation. Channels of multiple buffers and associated processors provide implement read and write instructions received at the interface. Multiple access modes are provided to read and write to system memory and to store sequences of commands in the provided buffers and to execute those stored sequences using an associated processor. By writing a…

Concurrent design process

Granted: August 1, 2017
Patent Number: 9721052
The present disclosure relates to a system and method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include displaying, at a first client computing device associated with a first user, at least a portion of an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner. Embodiments may further include processing a command at the first client computing device from…