Method and Apparatus for Optimizing Memory-Built-In-Self Test
Granted: March 27, 2014
Application Number:
20140089874
Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an…
CONTROLLED TOGGLE RATE OF NON-TEST SIGNALS DURING MODULAR SCAN TESTING OF AN INTEGRATED CIRCUIT
Granted: March 20, 2014
Application Number:
20140082421
A method is provided to test a modular integrated circuit (IC) comprising: testing a module-under-test (MUT) within the IC while causing a controlled toggle rate within a first neighbor module of the MUT; wherein the controlled toggle rate within the first neighbor module is selected so that toggling within the first neighbor module has substantially the same effect upon operation of the MUT that operation of the first neighbor module would have during actual normal functional operation…
SYSTEM AND METHOD FOR MODIFYING A DATA SET OF A PHOTOMASK
Granted: March 6, 2014
Application Number:
20140068527
The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.
DETERMINING AN OPTIMAL GLOBAL QUANTUM FOR AN EVENT-DRIVEN SIMULATION
Granted: March 6, 2014
Application Number:
20140067358
An apparatus and method for determining an optimal global quantum value for use in event-driven simulations of a device are disclosed herein. The device is simulated using information representative of a device design corresponding to the device, the simulation of the device comprising an event-driven simulation using a provisional global quantum value. Events included in a sequence chart corresponding to the simulation using the provisional global quantum value are compared against…
INTEGRATED CIRCUIT SIMULATION USING ANALOG POWER DOMAIN IN ANALOG BLOCK MIXED SIGNAL
Granted: December 19, 2013
Application Number:
20130338991
A method is provided that comprises a circuit design that includes multiple design blocks; a power intent specification file that defines a power domain within the circuit design and that identifies design instances within the power domain and that defines a control function to selectively transition the defined power domain between multiple respective power supply values; using a digital simulator to simulate operation of the digital representation while using an analog simulator to…
ANALOG/DIGITAL PARTITIONING OF CIRCUIT DESIGNS FOR SIMULATION
Granted: December 5, 2013
Application Number:
20130326440
For increasing user control and insight into preparing a mixed semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignments of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among…
METHOD AND SYSTEM FOR AUTOMATICALLY ESTABLISHING HIERARCHICAL PARAMETERIZED CELL (PCELL) DEBUGGING ENVIRONMENT
Granted: November 7, 2013
Application Number:
20130298092
A system and method are provided for establishing an automated debugging environment in an Electronic Design Automation (EDA) work flow for the debugging of parameterized cells (PCELLS/PyCELLS) in a layout. A user may merely select a particular PCELL within a hierarchical PCELL and the system and method will determine dependencies thereof. The source code for the selected PCELL and its dependencies may be located and loaded. At least one breakpoint may be set in the source code of the…
SYNCHRONIZED THREE-DIMENSIONAL DISPLAY OF CONNECTED DOCUMENTS
Granted: October 31, 2013
Application Number:
20130290834
A system and method for synchronizing the display and edit of a plurality of connected layouts or documents within a single display. A first document or plurality of elements may be displayed as active and a second document or plurality of elements may be displayed as non-active background in a first window. The second document or plurality of elements may be displayed as active and the first document or plurality of elements may be displayed as non-active background in a second window.…
SYNCHRONIZED THREE-DIMENSIONAL DISPLAY OF CONNECTED DOCUMENTS
Granted: September 19, 2013
Application Number:
20130246900
A system and method for synchronizing the display and edit of a plurality of connected layouts or documents within a single display. A first document or plurality of elements may be displayed as active and a second document or plurality of elements may be displayed as non-active background in a first window. The second document or plurality of elements may be displayed as active and the first document or plurality of elements may be displayed as non-active background in a second window.…
RECORDING AND PLAYBACK OF TRACE AND VIDEO LOG DATA FOR PROGRAMS
Granted: August 29, 2013
Application Number:
20130227350
Recording and playback of trace log data and video log data for programs is described. In one aspect, a method for viewing log data recorded during execution of a program includes causing a display of recorded images depicting prior visual user interaction with the program during a particular time period. The method also includes causing a display of messages tracing and describing prior execution of the program during the particular time period. The display of the messages and the…
DUAL-PATTERN COLORING TECHNIQUE FOR MASK DESIGN
Granted: July 25, 2013
Application Number:
20130191793
A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes…
METHOD AND SYSTEM FOR IMPLEMENTING GRAPHICALLY EDITABLE PARAMETERIZED CELLS
Granted: April 18, 2013
Application Number:
20130097572
Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design.
SHOOTING PNOISE CIRCUIT SIMULATION WITH FULL SPECTRUM ACCURACY
Granted: March 28, 2013
Application Number:
20130080126
An apparatus and method for performing periodic noise (Pnoise) simulation with full spectrum accuracy is disclosed herein. Noise contributions of a circuit under consideration are identified and separated for different computation treatment. The different computation treatment results in computational efficiency without sacrificing accuracy of simulation results.
METHOD AND APPARATUS FOR HIGH SPEED CACHE FLUSHING IN A NON-VOLATILE MEMORY
Granted: January 24, 2013
Application Number:
20130024623
An invention is provided for performing flush cache in a non-volatile memory. The invention includes maintaining a plurality of free memory blocks within a non-volatile memory. When a flush cache command is issued, a flush cache map is examined to obtain a memory address of a memory block in the plurality of free memory blocks within the non-volatile memory. The flush cache map includes a plurality of entries, each entry indicating a memory block of the plurality of free memory blocks.…
System and Method For Controlling Granularity of Transaction Recording In Discrete Event Simulation
Granted: January 17, 2013
Application Number:
20130018644
A method and system for controlling granularity of transaction recording and visualizing system performance and behavior in a discrete functional verification software simulation environment is disclosed. According to one embodiment, a simulation of a model is run in a discrete event simulation system for a period of time. During the simulation, statistical values of attribute for a plurality of transactions occurring during the period of time are monitored. Based on a granularity…
METHOD AND SYSTEM FOR IMPLEMENTING PARALLEL EXECUTION IN A COMPUTING SYSTEM AND IN A CIRCUIT SIMULATOR
Granted: December 13, 2012
Application Number:
20120316858
A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and…
SYSTEM AND METHOD FOR DYNAMICALLY INJECTING ERRORS TO A USER DESIGN
Granted: December 13, 2012
Application Number:
20120317533
A method and system for dynamically injecting errors to a user design is disclosed. In one embodiment, the user design having internal states and parameters is run in a design verification system. A reconfigurable design monitor monitors a plurality of error conditions based on the internal states and parameters of the user design and generates a trigger event when a predefined error condition is met. The reconfigurable design monitor transmits a trigger event to an error injector. The…
METHOD AND SYSTEM FOR IMPLEMENTING TOP DOWN DESIGN AND VERIFICATION OF AN ELECTRONIC DESIGN
Granted: December 6, 2012
Application Number:
20120311513
Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as “top-down” design verification. With the present stepwise refinement approach, the electronic design can be acted upon at different levels of abstraction, but with approximately the same level of resolution at each abstraction level. A strong relationship of consistency exists between the successive abstraction levels of the design.…
METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT
Granted: October 25, 2012
Application Number:
20120272201
A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT
Granted: October 25, 2012
Application Number:
20120272200
A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
