Method, product, and system for rapid sequence classification through a coverage model
Granted: September 24, 2024
Patent Number:
12099791
An approach is disclosed herein for test sequence processing that is applicable to machine learning model generated test sequences as disclosed herein. The test sequence processing includes classification, grouping, and filtering. The classification is generated based on the execution of the test sequences. The grouping is performed based on information captured during the classification of the test sequences. The filtering is performed on a group by group basis to remove redundant test…
Circuit design modification using timing-based yield calculation
Granted: September 10, 2024
Patent Number:
12086529
Various embodiments provide for using a timing-based yield calculation to modify a circuit design, which can be part of an electronic design automation (EDA) system. For instance, some embodiments use a timing-based yield calculation to modify one or more portions of the circuit design to improve timing of the circuit design (e.g., slack, slew, delay, etc.), the timing-based yield calculation of the circuit design, or both.
Circuit and method to set delay between two periodic signals with unknown phase relationship
Granted: August 27, 2024
Patent Number:
12072732
A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other. One or more phase signals is generated based on the master signal, the phase signals having different phases from each other. One of these phase signals is selected based on the phase of the first signal and a target phase delay between the first signal and second…
Post-CTS insertion delay and skew target reformulation of clock tree
Granted: August 13, 2024
Patent Number:
12061857
Methods and systems for performing post clock tree synthesis (CTS) of a clock tree include accessing, from memory, an integrated circuit design comprising a clock tree interconnecting a clock source to a plurality of clock sinks. Each clock sink has an associated current insertion delay. A mean insertion delay of the plurality of clock sinks is determined based on the associated current insertion delays of the clock sinks. A target insertion delay for the clock sinks is set based on the…
Live offset cancellation of the decision feedback equalization data slicers
Granted: August 6, 2024
Patent Number:
12057975
A receiver utilizes loop-unrolled decision feedback equalization (DFE). For each sample, two comparators, each configured with different thresholds, sample an input signal. The output of one of these comparators is selected and used as the output of the receiver and may be optionally input to additional DFE circuitry. The output of the other (non-selected) comparator is used to adjust an input offset voltage of that same comparator. Adjustments to the offset voltages of the comparators…
Memory interface mapping
Granted: August 6, 2024
Patent Number:
12057192
System connections map interface connections between the memory device and the memory controller. The memory controller is configured with information about these ‘mapped’ connections. The memory controller uses the mapping information to: correctly present commands and addresses to the memory device, perform CA training on mapped connections, generate read training data that accounts for mapped connections, correctly address mapped memory device pins for write training per pin…
Memory interface training
Granted: August 6, 2024
Patent Number:
12056394
A command/address (CA) interface of a memory controller coupled to a memory component is trained (e.g., voltages and timings are adjusted to maximize signal eye opening, sample timing margins etc.) while the CA interface is operated at highest known supported controller PHY frequency. After the CA interface has been trained at highest known supported controller PHY frequency, vendor specific information (e.g., vendor ID number, clock configuration, VDDQ configuration, etc.) is read from…
3D stacked die testing structure
Granted: August 6, 2024
Patent Number:
12055586
Methods and systems are provided for testing three-dimensional (3D) stacked dies of integrated circuits (ICs). The methods and systems receive, by test signal routing logic implemented on a first die, a first die test signal, the test signal routing logic operating in an elevate mode or turn mode. The methods and systems receive a second die test signal from a second die and route the first die test signal to an external device in the turn mode. The methods and systems route the second…
System, method, and computer program product for analog and mix-signal circuit placement
Granted: July 23, 2024
Patent Number:
12045730
The present disclosure relates to a computer-implemented method for genetic placement of analog and mix-signal circuit components. Embodiments may include receiving an unplaced layout associated with an electronic circuit design and grouping requirements. Embodiments may also include identifying one or more instances that need to be placed in the unplaced layout and areas of the unplaced layout configured to receive the instances. Embodiments may further include analyzing one or more…
Clock distribution architecture
Granted: July 16, 2024
Patent Number:
12040798
Embodiments included herein are directed towards a voltage-temperature drift resistant and power efficient clock distribution circuit. Embodiments may include a current generator and a voltage generator configured to receive an input from the current generator. Embodiments may also include a regulator which may be configured to receive a reference voltage from the voltage generator as an input and to generate regulated voltage as output. The clock distribution path may operate on a…
Systems and methods for scan chain stitching
Granted: June 11, 2024
Patent Number:
12007440
This disclosure relates scan chain stitching. In one example, scan chain elements from a scan chain element space can be received for a scan chain partition. The scan chain elements can be grouped based on scan chain element grouping criteria to form scan chain groups. Scan chain data identifying a number of scan chains for the scan chain partition can be received. The scan chains can be scan chain balanced across the scan chain groups to assign each scan chain to one of the scan chain…
Load-store unit dual tags and replays
Granted: May 14, 2024
Patent Number:
11983538
Techniques are disclosed relating to a processor load-store unit. In some embodiments, the load-store unit is configured to execute load/store instructions in parallel using first and second pipelines and first and second tag memory arrays. In tag write conflict situations, the load-store unit may arbitrate between the first and second pipelines to ensure the first and second tag memory array contents remain identical. In some embodiments, a data cache tag replay scheme is utilized. In…
High-speed serial link signal chain
Granted: May 7, 2024
Patent Number:
11979264
Methods and systems are provided for processing a signal over a serial link. The methods and systems receive, by an adjustable filter, a serial input signal, the adjustable filter configured to set a corner frequency of a channel response and a gain of the channel response, the adjustable filter adding a zero to the channel response before to a pole of the serial input signal. The methods and systems selectively apply, by a bandwidth booster component, compensation to signal attenuation…
Identifying and training floating tap for decision feedback equalization
Granted: May 7, 2024
Patent Number:
11979262
Various embodiments provide for identifying and training a floating tap for decision feedback equalization. For some embodiments, the identification and training of the floating tap described herein can be part of a circuit for receiver block of a system, such as a memory system.
Memory view for non-volatile memory module
Granted: April 30, 2024
Patent Number:
11971818
A memory view generator evaluates a Liberty file characterizing an NVM module to generate a memory view file for the NVM module. The memory view file includes a port alias identifying ports of the NVM module. The port alias for a set of ports of the NVM module characterizes a type of port in the set of ports. The memory view file includes a port action identifying ports of the NVM module that have a static value and a port access identifying ports of the NVM module that have a dynamic…
Control algorithm generator for non-volatile memory module
Granted: April 23, 2024
Patent Number:
11966633
An NVM algorithm generator that evaluates a Liberty file characterizing an NVM module and a memory view of the NVM module that identifies ports and associated operations of the NVM module to generate a control algorithm. The control algorithm includes a read algorithm that includes an order of operations for assigning values to ports of the NVM module to assert a read condition of a strobe port, executing a memory read on the NVM module and setting values to the ports on the NVM module…
Method and system to implement a composite, multi-domain model for electro-optical modeling and simulation
Granted: April 16, 2024
Patent Number:
11960809
Provided is an improved method, system, and computer program product to implement simulation for photonic devices. A composite, multi-domain simulation model is disclosed, with connected domain-specific representations that allow the use of the most relevant simulator technology for a given domain. The model has external connection points either expressed as actual ports or virtual ones, embodied by simulator API calls in the model.
Managing multiple cache memory circuit operations
Granted: April 16, 2024
Patent Number:
11960400
A cache memory circuit capable of dealing with multiple conflicting requests to a given cache line is disclosed. In response to receiving an acquire request for the given cache line from a particular lower-level cache memory circuit, the cache memory circuit sends probe requests regarding the given cache line to other lower-level cache memory circuits. In situations where a different lower-level cache memory circuit is simultaneously trying to evict the given cache line at the particular…
System and method for poison information propagation in a storage device
Granted: April 16, 2024
Patent Number:
11960351
Systems and methods for propagating poison information are provided. Embodiments include receiving write data having a poison flag asserted indicating the data to be written to a memory device is erroneous. Embodiments further include converting the write data to a pre-fixed data pattern and generating a parity code, based upon, at least in part, the pre-fixed data pattern. Embodiments may also include injecting a correctable error into the write-data or parity code and writing the write…
Test-point flop sharing with improved testability in a circuit design
Granted: April 2, 2024
Patent Number:
11947887
A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that is configured to evaluate the circuit netlist to determine compatibility of the test-point nodes in the circuit netlist. The test-point flop allocation module can further allocate each of the test-point flops to a…
