Queue circuit for controlling access to a memory circuit
Granted: November 12, 2024
Patent Number:
12141474
A queue circuit that manages access to a memory circuit in a computer system includes multiple sets of entries for storing access requests. The entries in one set of entries are assigned to corresponding sources that generate access requests to the memory circuit. The entries in the other set of entries are floating entries that can be used to store requests from any of the sources. Upon receiving a request from a particular source, the queue circuit checks the entry assigned to the…
Method, system, and computer program product for characterizing an electronic circuit using model order reduction-based envelope fourier techniques
Granted: November 12, 2024
Patent Number:
12141233
Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with an MOR-based envelope Fourier technique. Multiple training models may be determined at multiple time points for an electronic circuit by using at least the MOR-based envelope Fourier technique that comprises a harmonic balance technique. A training model of the multiple training models may be reduced into a reduced order training model in a reduced order space at least by applying at…
Extended-burst write training
Granted: October 15, 2024
Patent Number:
12119080
A control component transmits a timing strobe and associated write data burst to a memory component, extending the write data burst to include a quantity of successive bits in excess of active edges in the timing strobe to ensure that the write data burst is sampled under worst-case timing skew conditions.
Prefetch circuit for cache memory
Granted: October 8, 2024
Patent Number:
12111765
A prefetch circuit coupled to a cache memory circuit includes a storage circuit that stores multiple virtual-to-physical address map entries. In response to receiving an indication of a miss for an access request to the cache memory circuit, the prefetch circuit generates a prefetch address and compares it to a demand address included in the access request. In response to determining that the demand address and the prefetch address are in different memory pages, the prefetch circuit…
Thin-oxide voltage level shifter
Granted: October 1, 2024
Patent Number:
12107578
Methods and systems are provided for performing voltage level shifting using thin-oxide devices. The methods and systems convert an input signal associated with a first voltage domain to output signals associated with the first and second voltage domains. A first set of thin-oxide devices generate a first output signal at the high-level voltage signal when the input signal comprises a high logic level and generate the first output signal at a ground level voltage signal when the input…
Port generation based on layout connectivity information
Granted: October 1, 2024
Patent Number:
12106032
Various embodiments provide for port generation for a circuit design based on layout connectivity information, which can be used as part of an automatic or a semi-automatic process of an electronic design automation (EDA) system. For instance, various embodiments access connectivity information for one or more networks of a circuit design, and use the connectivity information to identify pins of signal networks as positive connections for ports, and geometric shapes on references…
Method, product, and system for rapid sequence classification through a coverage model
Granted: September 24, 2024
Patent Number:
12099791
An approach is disclosed herein for test sequence processing that is applicable to machine learning model generated test sequences as disclosed herein. The test sequence processing includes classification, grouping, and filtering. The classification is generated based on the execution of the test sequences. The grouping is performed based on information captured during the classification of the test sequences. The filtering is performed on a group by group basis to remove redundant test…
Circuit design modification using timing-based yield calculation
Granted: September 10, 2024
Patent Number:
12086529
Various embodiments provide for using a timing-based yield calculation to modify a circuit design, which can be part of an electronic design automation (EDA) system. For instance, some embodiments use a timing-based yield calculation to modify one or more portions of the circuit design to improve timing of the circuit design (e.g., slack, slew, delay, etc.), the timing-based yield calculation of the circuit design, or both.
Circuit and method to set delay between two periodic signals with unknown phase relationship
Granted: August 27, 2024
Patent Number:
12072732
A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other. One or more phase signals is generated based on the master signal, the phase signals having different phases from each other. One of these phase signals is selected based on the phase of the first signal and a target phase delay between the first signal and second…
Post-CTS insertion delay and skew target reformulation of clock tree
Granted: August 13, 2024
Patent Number:
12061857
Methods and systems for performing post clock tree synthesis (CTS) of a clock tree include accessing, from memory, an integrated circuit design comprising a clock tree interconnecting a clock source to a plurality of clock sinks. Each clock sink has an associated current insertion delay. A mean insertion delay of the plurality of clock sinks is determined based on the associated current insertion delays of the clock sinks. A target insertion delay for the clock sinks is set based on the…
Live offset cancellation of the decision feedback equalization data slicers
Granted: August 6, 2024
Patent Number:
12057975
A receiver utilizes loop-unrolled decision feedback equalization (DFE). For each sample, two comparators, each configured with different thresholds, sample an input signal. The output of one of these comparators is selected and used as the output of the receiver and may be optionally input to additional DFE circuitry. The output of the other (non-selected) comparator is used to adjust an input offset voltage of that same comparator. Adjustments to the offset voltages of the comparators…
Memory interface mapping
Granted: August 6, 2024
Patent Number:
12057192
System connections map interface connections between the memory device and the memory controller. The memory controller is configured with information about these ‘mapped’ connections. The memory controller uses the mapping information to: correctly present commands and addresses to the memory device, perform CA training on mapped connections, generate read training data that accounts for mapped connections, correctly address mapped memory device pins for write training per pin…
Memory interface training
Granted: August 6, 2024
Patent Number:
12056394
A command/address (CA) interface of a memory controller coupled to a memory component is trained (e.g., voltages and timings are adjusted to maximize signal eye opening, sample timing margins etc.) while the CA interface is operated at highest known supported controller PHY frequency. After the CA interface has been trained at highest known supported controller PHY frequency, vendor specific information (e.g., vendor ID number, clock configuration, VDDQ configuration, etc.) is read from…
3D stacked die testing structure
Granted: August 6, 2024
Patent Number:
12055586
Methods and systems are provided for testing three-dimensional (3D) stacked dies of integrated circuits (ICs). The methods and systems receive, by test signal routing logic implemented on a first die, a first die test signal, the test signal routing logic operating in an elevate mode or turn mode. The methods and systems receive a second die test signal from a second die and route the first die test signal to an external device in the turn mode. The methods and systems route the second…
System, method, and computer program product for analog and mix-signal circuit placement
Granted: July 23, 2024
Patent Number:
12045730
The present disclosure relates to a computer-implemented method for genetic placement of analog and mix-signal circuit components. Embodiments may include receiving an unplaced layout associated with an electronic circuit design and grouping requirements. Embodiments may also include identifying one or more instances that need to be placed in the unplaced layout and areas of the unplaced layout configured to receive the instances. Embodiments may further include analyzing one or more…
Clock distribution architecture
Granted: July 16, 2024
Patent Number:
12040798
Embodiments included herein are directed towards a voltage-temperature drift resistant and power efficient clock distribution circuit. Embodiments may include a current generator and a voltage generator configured to receive an input from the current generator. Embodiments may also include a regulator which may be configured to receive a reference voltage from the voltage generator as an input and to generate regulated voltage as output. The clock distribution path may operate on a…
Systems and methods for scan chain stitching
Granted: June 11, 2024
Patent Number:
12007440
This disclosure relates scan chain stitching. In one example, scan chain elements from a scan chain element space can be received for a scan chain partition. The scan chain elements can be grouped based on scan chain element grouping criteria to form scan chain groups. Scan chain data identifying a number of scan chains for the scan chain partition can be received. The scan chains can be scan chain balanced across the scan chain groups to assign each scan chain to one of the scan chain…
Load-store unit dual tags and replays
Granted: May 14, 2024
Patent Number:
11983538
Techniques are disclosed relating to a processor load-store unit. In some embodiments, the load-store unit is configured to execute load/store instructions in parallel using first and second pipelines and first and second tag memory arrays. In tag write conflict situations, the load-store unit may arbitrate between the first and second pipelines to ensure the first and second tag memory array contents remain identical. In some embodiments, a data cache tag replay scheme is utilized. In…
Identifying and training floating tap for decision feedback equalization
Granted: May 7, 2024
Patent Number:
11979262
Various embodiments provide for identifying and training a floating tap for decision feedback equalization. For some embodiments, the identification and training of the floating tap described herein can be part of a circuit for receiver block of a system, such as a memory system.
High-speed serial link signal chain
Granted: May 7, 2024
Patent Number:
11979264
Methods and systems are provided for processing a signal over a serial link. The methods and systems receive, by an adjustable filter, a serial input signal, the adjustable filter configured to set a corner frequency of a channel response and a gain of the channel response, the adjustable filter adding a zero to the channel response before to a pole of the serial input signal. The methods and systems selectively apply, by a bandwidth booster component, compensation to signal attenuation…
