Method, product, and system for a sequence generation ecosystem using machine learning
Granted: March 4, 2025
Patent Number:
12242784
An approach is disclosed herein a sequence generation ecosystem using machine learning. The approach disclosed herein is a new approach to sequence generation in the context of validation that relies on machine learning to explore and identify ways to achieve different states. In particular, the approach divides the valid operations into different respective actions and action sequences. These actions are selected by machine learning models as they are being trained using online…
Method and system for dynamic windows traffic in emulation systems
Granted: February 18, 2025
Patent Number:
12229043
Systems and methods of collecting performance metrics of an emulated design are disclosed. A method includes receiving, by a processor in the emulation system from a host system, configuration data including one or more user defined parameters, connecting, by the processor, a performance monitor to a port between communicatively connected components in the emulation system, initiating, by the processor, an emulation of the DUT, receiving, by the processor, emulation data from the…
System, method, and computer program product for optimization-based printed circuit board design
Granted: February 11, 2025
Patent Number:
12223248
The present disclosure relates to electronic circuit design, and more specifically, to training a neural network to serve as the reward function for optimization-based approaches to PCB design automation. Embodiments may include generating, using a processor, one or more placed designs using a genetic optimization methodology including a reward function and adjusting the one or more placed designs and the reward function during the generating. Embodiments may further include routing the…
System and method for interactive visualization of placement of objects in an electronic design
Granted: February 11, 2025
Patent Number:
12223244
Embodiments included herein are directed towards a method for visualizing an electronic circuit design. Embodiments may include causing a display of a portion of an electronic design at a graphical user interface and receiving, at the graphical user interface, a selection of an object to be moved, wherein the object is displayed in a first color. In response to a user input, embodiments may include moving the object at the graphical user interface nearer a target location, displaying at…
Clock recovery for PAM4 signaling using bin-map
Granted: February 4, 2025
Patent Number:
12218786
A technical solution is directed to a clock recovery apparatus for multi-level signaling on a single-lane communication interface. The apparatus can use bin-map logic to successfully recover a common clock per symbol received on the multi-level signal interface. The multi-level signal can be PAM4 signaling where two bits are encoded to represent four levels. The clock recovery apparatus can detect signal level through individual edge detectors for each of the two bits and can handle…
Maximum turn constraint for routing of integrated circuit designs
Granted: February 4, 2025
Patent Number:
12216977
Aspects of the present disclosure address systems and methods for routing an integrated circuit design based on a maximum turn constraint. Data describing an integrated circuit is accessed. The integrated circuit design comprises a net specifying a connection between a first pin and a second pin. A maximum turn constraint is accessed. The maximum turn constraint specifies a maximum number of turns for connection paths generated in routing the integrated circuit design. The net is routed…
Interface device
Granted: January 28, 2025
Patent Number:
12212315
Methods and systems are provided for transmitting data using thin-oxide devices. The methods and system generate a first bias voltage and a second bias voltage based on a power supply voltage of the second voltage domain, the first bias voltage value representing a high-level voltage signal of the first voltage domain, and the second bias voltage representing a low-level voltage signal of the second voltage domain and its value corresponds to a difference between the second voltage…
System and method for verifying a cross-connection of lanes in a multi-lane environment using a single testbench
Granted: January 21, 2025
Patent Number:
12204423
An approach for verifying a cross-connection of lanes in a multi-lane environment using a single testbench-is provided. The approach may include providing a physical receiver lane index associated with a local device and providing a physical transmitter lane index associated with a peer device. The approach may further include randomizing a number of connected receiver lanes associated with the local device and a number of connected receiver lanes associated with the peer device. The…
Wireline receiver sampling circuit
Granted: January 21, 2025
Patent Number:
12206532
Embodiments included herein are directed towards sampling circuits and methods of using the same. Embodiments may include a data sense amplifier circuit and a reference sense amplifier circuit directly connected with the data sense amplifier circuit. Embodiments may further include a latch circuit configured to receive a first input from the data sense amplifier circuit and a second input from the reference sense amplifier circuit. The latch circuit may be further configured to generate…
Read data strobe path having variation compensation and delay lines
Granted: January 21, 2025
Patent Number:
12205673
Various embodiments described herein provide for a read data strobe (RDQS) path having variation compensation (e.g., voltage and temperature compensation), delay lines, or both, where the RDQS path can be included by a physical (PHY) interface for a memory device, such as a Double Data Rate (DDR) Dynamic Random-Access Memory (DRAM) memory device.
High accuracy timestamping of transmissions at physical layer of communication devices and systems
Granted: January 14, 2025
Patent Number:
12199770
A method can include obtaining, at a physical communication layer integrated with a communication interface, a data packet, detecting, by a detection circuit integrated with the physical communication layer, a portion of data in the data packet corresponding to a marker identifying the data packet, linking, by the physical communication layer based on the marker, a timestamp with the data packet, and transmitting, by the physical communication layer, the data packet linked with the…
Clock duty cycle measurement
Granted: December 31, 2024
Patent Number:
12184286
The present disclosure describes a circuit that may include a first amplifier portion configured to receive a first input signal corresponding to a first clock signal and a second input signal corresponding to a second clock signal. The circuit may include a first amplifier of the first amplifier portion. The first amplifier may be configured to receive a first amplifier input signal and a second amplifier input signal. The circuit may include a second amplifier portion configured to…
System and method for write clock double data rate duty cycle correction
Granted: December 31, 2024
Patent Number:
12183427
The present disclosure relates to a system and method for duty cycle correction is provided. The method may include receiving a signal at a duty cycle adjuster and performing serializer clock duty cycle correction at the duty cycle adjuster. The method may further include performing true clock duty cycle correction at a transmitter duty cycle adjuster and performing complementary duty cycle distortion correction at the transmitter duty cycle adjuster.
Systems and methods for exporting design data using near-optimal multi-threading scheme
Granted: December 31, 2024
Patent Number:
12182613
A system for generating a single design data file may include a processor and a memory. The processor may obtain design data including a plurality of design units. The processor may determine a first order of the plurality of design units. The processor may translate each of the plurality of design units into a corresponding file fragment by executing multiple threads of a first process. The processor may aggregate each of the plurality of file fragments into the single design data file…
Embedded processor architecture with shared memory with design under test
Granted: December 31, 2024
Patent Number:
12182485
A shared memory is provided between simulation processors and emulation processors within an emulation chip. The shared memory is configured to enable the simulation processors and the emulation processors to exchange simulation data and emulation data respectively with each other during simulation and emulation operations. The simulation processors and the emulation processors may update their respective simulation and emulation operations in response to the simulation data and the…
System and method for creating a high-level parameter relational data model for memory configurability solutions
Granted: December 31, 2024
Patent Number:
12182020
Embodiments are directed towards a method for creating a relational memory designed for one or more key parameters in at least one memory part configurations library. The method may include identifying one or more high-level parameters (HLPs) within the at least one memory part configurations library, assigning each non-HLP parameter an HLP key, using the assigned HLP keys as a frame of reference to cross-correlate each non-HLP parameter with every other non-HLP parameter in the at least…
Memory circuit with power registers
Granted: December 31, 2024
Patent Number:
12182016
A memory circuit may include both an array circuit and multiple register circuits, where the power to retrieve data from one of the register circuits may be less than the power to retrieve data from the array circuit. The array circuit may store multiple data words, and the multiple register circuits may be configured to store a subset of the multiple data words. During a first cycle, a read command and an address may be received. In response to a determination that the address…
Fragmented periodic timing calibration
Granted: November 26, 2024
Patent Number:
12153528
Periodic signal timing calibration is implemented in time-distributed fragments executed concurrently with occasional system-idling maintenance operations to maintain reliable synchronous communication between interconnected system components without impacting system availability.
Method, system, and computer program product for characterizing an electronic circuit using model order reduction-based envelope fourier techniques
Granted: November 12, 2024
Patent Number:
12141233
Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with an MOR-based envelope Fourier technique. Multiple training models may be determined at multiple time points for an electronic circuit by using at least the MOR-based envelope Fourier technique that comprises a harmonic balance technique. A training model of the multiple training models may be reduced into a reduced order training model in a reduced order space at least by applying at…
Queue circuit for controlling access to a memory circuit
Granted: November 12, 2024
Patent Number:
12141474
A queue circuit that manages access to a memory circuit in a computer system includes multiple sets of entries for storing access requests. The entries in one set of entries are assigned to corresponding sources that generate access requests to the memory circuit. The entries in the other set of entries are floating entries that can be used to store requests from any of the sources. Upon receiving a request from a particular source, the queue circuit checks the entry assigned to the…
