Sampler with built-in DFE and offset cancellation
Granted: June 13, 2023
Patent Number:
11677593
Various embodiments provide for a data sampler with built-in decision feedback equalization (DFE) and offset cancellation. For some embodiments, two or more data samplers described herein can be used to implement a data signal receiver circuit, which can use those two or more data samplers to facilitate half-rate or quarter-rate data sampling.
Method, product, and apparatus for a machine learning process leveraging input sparsity on a pixel by pixel basis
Granted: June 13, 2023
Patent Number:
11676068
An approach includes a method, product, and apparatus for dynamically removing sparse data on a pixel by pixel basis. In some embodiments, a machine learning processing job is received. The machine learning processing job is then executed on a pixel by pixel basis by selecting non-zero data values for input into a systolic array, wherein sparse data is not selected for input into the systolic array. Subsequently, a message is generated that provides an indication of whether the execution…
Pruning redundant buffering solutions using fast timing models
Granted: June 13, 2023
Patent Number:
11675956
A system includes a machine configured to perform operations including accessing an integrated circuit design including a buffer tree that interconnects a plurality of inputs and buffers. The buffer tree includes a baseline timing characteristic. The operations include identifying a set of candidate solutions for improving the baseline timing characteristic using an initial timing model and selecting a subset of candidate solutions that have a timing characteristic lower than the…
Routing using rule-based blockage extension
Granted: June 13, 2023
Patent Number:
11675955
Various embodiments provide for routing a net of a circuit design using rule-based routing blockage extension, which may be part of electronic design automation (EDA). In particular, some embodiments route a net of a circuit design by determining a dimension extension value based on a design rule of the circuit design and applying the dimension extension value to at least one existing routing blockage.
Systems and methods of buffering and accessing input data for convolution computations
Granted: June 6, 2023
Patent Number:
11669725
Using a buffer sized according to the size of the filters of a convolutional neural network (CNN), a processor may use a read pointer to generate a two-dimensional virtual matrix of inputs. The number of inputs in each row in the two-dimensional virtual matrix of inputs may match the one-dimensional filter size of the cubic filters. The processor may collapse each of the cubic filters to one-dimensional linear arrays and generate a two-dimensional filter matrix from the one-dimensional…
System and method for memory management
Granted: May 30, 2023
Patent Number:
11663149
Embodiments include herein are directed towards a dynamic random access memory system. Embodiments may include a command queue that is configured to hold all commands that are currently selectable for bank operation and execution. Embodiments may further include bank logic operatively connected with the command queue. The bank logic may include a bank management module and a plurality of bank slices, wherein each of the plurality of bank slices is an independent, re-assignable bank…
Removal of dependent instructions from an execution pipeline
Granted: May 23, 2023
Patent Number:
11656876
Techniques are disclosed relating to an apparatus, including a data storage circuit having a plurality of entries, and a load-store pipeline configured to allocate an entry in the data storage circuit in response to a determination that a first instruction includes an access to an external memory circuit. The apparatus further includes an execution pipeline configured to make a determination, while performing a second instruction and using the entry in the data storage circuit, that the…
Method, product, and apparatus for a machine learning process using dynamic rearrangement of sparse data and corresponding weights
Granted: May 16, 2023
Patent Number:
11651283
An approach is described for a method, product, and apparatus for a machine learning process using dynamic rearrangement of sparse data and corresponding weights. This approach includes a method, product, and apparatus for dynamically rearranging input data to move sparse data to a location such that computations on the sparse data might be avoided when executing a machine learning processing job. For example, sparse data within each row of the input matrix can be moved to the end of…
Machine-learning based clustering for clock tree synthesis
Granted: May 9, 2023
Patent Number:
11645441
Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of clock sinks during clock tree synthesis. An integrated circuit (IC) design comprising a clock net that includes a plurality of clock sinks is accessed. An initial number of clusters to generate from the set of clock sinks is determined using a machine-learning model. A first set of clusters is generated from the set of clocks sinks and includes the initial number of…
Machine-learning based clustering for clock tree synthesis
Granted: May 9, 2023
Patent Number:
11645441
Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of clock sinks during clock tree synthesis. An integrated circuit (IC) design comprising a clock net that includes a plurality of clock sinks is accessed. An initial number of clusters to generate from the set of clock sinks is determined using a machine-learning model. A first set of clusters is generated from the set of clocks sinks and includes the initial number of…
Programmable fractional ripple divider
Granted: April 18, 2023
Patent Number:
11632119
Embodiments included herein are directed towards a fractional feedback divider circuit and associated method. The circuit may include a programmable feedback divider including a plurality of flip-flops arranged in series. The programmable feedback divider may be configured to receive an input clock signal and a reset signal comprising at least one pulse and to generate a divided clock. The circuit may include reset logic configured to receive an input from the programmable feedback…
Constraint-based dynamic quantization adjustment for fixed-point processing
Granted: April 18, 2023
Patent Number:
11630982
Aspects of the present disclosure address systems and methods for fixed-point quantization using a dynamic quantization level adjustment scheme. Consistent with some embodiments, a method comprises accessing a neural network comprising floating-point representations of filter weights corresponding to one or more convolution layers. The method further includes determining a peak value of interest from the filter weights and determining a quantization level for the filter weights based on…
Failure mode analysis for circuit design
Granted: April 18, 2023
Patent Number:
11630938
Various embodiments provide for failure mode analysis of a circuit design, which can be used as part of electronic design automation (EDA). In particular, some embodiments provide for failure mode analysis of a circuit design by determining a set of functional primitives of a circuit design component (e.g., cell at gate level) that contribute to a root cause logic for a specific failure mode.
High speed differential input single phase clock flip-flop
Granted: April 11, 2023
Patent Number:
11626863
The present disclosure relates to a high speed, differential input, single phase clock circuit. The circuit may include a cross-coupled PMOS connected with a cross-coupled NMOS via a pass gate. The circuit may further include a single-phase clock in communication with the cross-coupled PMOS and the cross-coupled NMOS. The circuit may also include a master and a slave each having an output node that charges and discharges to VDD or ground respectively, wherein there is no direct feedback…
Grouping cells in cell library based on clustering
Granted: April 11, 2023
Patent Number:
11625525
Various embodiments provide for clustering-based grouping of cells in a cell library, which can be used for pruning the cell library. In particular, various embodiments provide for a clustering-based grouping of cells in a cell library based on a criterion (or cell attribute), and for pruning of the cell library based on the grouping of cells, which can optimize the cell library for the criterion. For instance, some embodiments provide for a clustering-based grouping of cells based on…
Partitioned UFP for displayport repeater
Granted: April 4, 2023
Patent Number:
11620251
Methods and systems are disclosed for an upstream facing port implementation for DisplayPort link-training tunable PHY repeaters (LTTPRs). The device includes an upstream facing port to interface with an external DisplayPort source device and a downstream facing port to interface with an external DisplayPort sink device and the upstream facing port. The upstream facing port is configured to perform operations including receiving a main link data stream from an external transmitting…
Post-CTS clock tree restructuring
Granted: April 4, 2023
Patent Number:
11620428
Various embodiments provide a system for performing operations that comprise accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a present timing offset of the clock tree to a target timing offset. In response, a group of clock sinks to be adjusted are identified to satisfy the request. The clock tree is then modified by moving a terminal of the group from a…
System, method, and computer program product for predicting parasitics in an electronic design
Granted: April 4, 2023
Patent Number:
11620548
The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having an original schematic associated therewith and extracting one or more features for each net from the schematic. Embodiments may include storing one or more resistance or capacitance values for each net and applying the one or more resistance or capacitance values as labels for a machine learning…
Post-CTS clock tree restructuring
Granted: April 4, 2023
Patent Number:
11620428
Various embodiments provide a system for performing operations that comprise accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a present timing offset of the clock tree to a target timing offset. In response, a group of clock sinks to be adjusted are identified to satisfy the request. The clock tree is then modified by moving a terminal of the group from a…
User interface for interactive skew group analysis
Granted: April 4, 2023
Patent Number:
11620417
Aspects of the present disclosure address systems, methods, and a user interface for providing interactive skew group visualizations for integrated circuit (IC) design. The method includes causing display of a user interface that includes a display of a grouped view of a clock-tree including a plurality of skew group indicators. The method further includes receiving a user selection of a skew group indicator and updating the user interface to display a detailed view of the skew group…
