Detecting indexing errors in declarative languages
Granted: July 2, 2013
Patent Number:
8479167
A method for detecting program code errors including searching for lines of command codes in the program code. A line of command code includes command codes and indices. The lines of command codes are organized as paragraphs. At least one of the lines of commands codes in each paragraph is different from the other lines of commands codes in the paragraph. The method further including separating the command codes from the indices for the lines of command codes, wherein the indices are a…
Method and apparatus for automatically fixing double patterning loop violations
Granted: June 25, 2013
Patent Number:
8473874
A method for automatically generating and prioritizing several design solutions that resolve a double patterning (DP) loop violation in an IC design layout. The method of some embodiments receives a DP loop violation marker and identifies pairs of edges of shapes that form a double patterning loop based on the DP loop violation marker. For each pair of edges that violates the design rule, the method generates one or more design solutions. Each design solution moves a single edge or both…
System and method for providing multi-process protection using direct memory mapped control registers
Granted: June 25, 2013
Patent Number:
8473661
A method and system for providing multi-process protection using direct memory mapped control registers is disclosed. According to one embodiment, a computer-implemented method provides a set of control registers for each execution unit of a plurality of execution units in a controller switch. The controller switch facilitates communication between a host system and one or more devices connected to a plurality of device ports of the controller switch. A device driver is provided to allow…
Method and system for reducing switching activity during scan-load operations
Granted: June 18, 2013
Patent Number:
8468404
A method and system for reducing switching activity of a spreader network during a scan-load operation is disclosed. According to one embodiment, a spreader network receives a plurality of scan input signals from a tester. A linear feedback shift register of the spread network is updated using the plurality of scan input signals. Each bit of the linear feedback shift register is shifted at each shift cycle for a plurality of shift cycles. The linear feedback shift register outputs a…
Hardware emulation unit having a shadow processor
Granted: June 18, 2013
Patent Number:
8468009
A hardware emulator having an emulation unit with a shadow processor is described. The shadow processor is capable of performing an extra look up table (LUT) operation in addition to the LUT operation performed by a processor within the emulation unit. The emulation unit comprises a memory for supplying a first amount of data to a shadow processor register, wherein the shadow processor register stores the first amount of data for later retrieval. The data stored in the shadow processor…
Method and system for routing optimally between terminals through intermediate vias in a circuit design
Granted: June 11, 2013
Patent Number:
8464196
A system and method are provided for establishing an automated routing environment in an electronic design automation (EDA) work flow for the routing of a circuit design. A user may merely specify a flow via pattern, a flow via location, and a start and end terminal and thereby, the auto router or path finder will automatically find the least-cost paths between each of the start terminals through at least one intermediate via of the flow via and ending at an end terminal. Upon successful…
Supporting dynamic aspects of polymorphism in high-level synthesis of integrated circuit designs
Granted: June 4, 2013
Patent Number:
8458630
A method for integrated circuit design is disclosed including determining if at least one dynamic class and at least one virtual function are present within a chip program description of an integrated circuit design; and if so then converting the at least one virtual function into a non-virtual function, generating at least one virtual pointer for the at least one dynamic class, converting at least one function calling the at least one virtual function into at least one conditional…
System and method for analyzing power consumption of electronic design undergoing emulation or hardware based simulation acceleration
Granted: May 28, 2013
Patent Number:
8453086
The invention described here is the methods of using a hardware-based functional verification system to mimic a design under test (DUT), under intended application environment and software, to record or derive the transition activities of all circuits of the DUT, then calculate the total or partial power consumption during the period of interest. The period of interest is defined by the user in terms of “events” which are the arbitrary states of the DUT. Furthermore, the user can…
Change tracking and incremental synchronization of EDA design and technology data
Granted: May 28, 2013
Patent Number:
8453136
A method and an apparatus are described for allowing several different applications to incrementally collaborate while making changes to a circuit design.
Method and mechanism for managing hierarchical data for implementing region query
Granted: May 28, 2013
Patent Number:
8453091
Disclosed is an improved approach for managing, tracking, and querying hierarchical data in layouts. According to some aspects, hierarchical grids are employed utilizing a scheme that organizes physical objects into a set of gradually refined grids that avoids the need to maintain duplicates while enhancing the desirable characteristics of existing schemes, including fast query times, fast data structure initialization and reduced memory footprint. Each grid-cell may be further…
System and method for adapting behavioral models to fluctuations in parametrically integrated environment
Granted: May 28, 2013
Patent Number:
8452582
A method and system are provided for parametrically adapting a behavioral model pre-configured for a preset supply reference level to fluctuations therein. The behavioral model is adaptively scaled for deviation of the electronic system supply reference from its preset level. The scaling includes reconstructing a surrogate device parametrically representative of a portion of the behavioral model's undisclosed circuit. The reconstruction includes pre-setting a transistor type for the…
Adaptive mesh resolution in electric circuit simulation and analysis
Granted: May 21, 2013
Patent Number:
8448117
An adaptive mesh of virtual nodes is provided to analyze the performance of a power/ground plane pair having an irregular shape. Plane transmission line characteristics and regional modal resonances can be modeled accurately, and with a significant decrease in simulation time as compared to traditional methods. A variable-sized cell structure is constructed with smaller cells in irregular regions and with larger cells in uniform regions. Grid nodes may thus stay aligned along length and…
Analog/digital partitioning of circuit designs for simulation
Granted: May 21, 2013
Patent Number:
8448116
For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among…
System, method, and computer program product for automatic power management verification
Granted: May 21, 2013
Patent Number:
8448112
The present disclosure relates to a computer-implemented method for automatically generating a power management verification component. The method may include receiving one or more inputs including a power intent definition. The method may further include automatically generating a power management verification environment based upon, at least in part, the power intent definition, the power management verification environment including at least one of a driver and a monitor.
Method and an apparatus to perform statistical static timing analysis
Granted: May 21, 2013
Patent Number:
8448104
A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners using a static timing analysis module, and estimating performance of the circuit at a predetermined confidence level based on results of the statistical analysis during an automated design flow of the circuit without using libraries…
Method and system for parallel processing of IC design layouts
Granted: May 21, 2013
Patent Number:
8448096
Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing…
Method and system for implementing a structure to implement I/O rings and die area estimations
Granted: May 14, 2013
Patent Number:
8443323
Disclosed are improved methods, systems, and computer program products for implementing an I/O ring structure to generate an I/O ring arrangement for an electronic design, and for performing chip planning and estimation based upon the I/O ring arrangement. Nodes in the I/O ring structure are used to track objects in the I/O ring.
Method of eliminating a lithography operation
Granted: May 14, 2013
Patent Number:
8440569
Methods of semiconductor device fabrication are disclosed. An exemplary method includes processes of depositing a first pattern on a semiconductor substrate, wherein the first pattern defines wide and narrow spaces; depositing spacer material over the first pattern on the substrate; etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of a wide space defined by the…
Methods for improved simulation of integrated circuit designs
Granted: May 7, 2013
Patent Number:
8438003
A method of improved simulator processing is provided. The method according to the current invention includes grouping frequently accessed data into one set id to improve memory hierarchy performance. The method further includes simulating predication in a non-predicated architecture to improve CPU performance. The simulated predication includes pseudo-predicated implementation of read-operation vector element access pseudo-predicated implementation of write-operation vector element…
Method and apparatus for improving small write performance in a non-volatile memory
Granted: May 7, 2013
Patent Number:
8438325
An invention is provided for improving performance in block based non-volatile memory when performing random small write operations. When requests for small page updates are received for a memory page currently storing data, the updated page data is written to a reserve memory page. The reserve memory page can be in the same memory block as the target memory page, or in an associated reserve memory block. In addition, the associated logical page address is temporarily remapped to the…
